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Table 2-22. Miscellaneous GTL+ AC Specifications
T35: Asynchronous GTL+ input pulse width
T36: PWRGOOD assertion to RESET# de-assertion
T37: BCLK stable to PWRGOOD assertion
T38: PROCHOT# pulse width
T39: THERMTRIP# assertion until V
T40: FERR# valid delay from STPCLK# deassertion
T41: V
stable to PWRGOOD assertion
CC
T42: PWRGOOD rise time
T43: V
CC_BOOT
T44: VID / BSEL valid to V
T48: V
stable to VID / BSEL valid
TT
T49: V
CCPLL
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing
Voltage (V
3.
These signals may be driven asynchronously.
4.
Refer to
5.
A minimum pulse width of 500 µs is recommended when FORCEPR# is asserted by the system
6.
Refer to the PWRGOOD signal definition in
7.
Length of assertion for PROCHOT# does not equal TCC activation time. Time is required after the assertion
and before the deassertion of PROCHOT# for the processor to enable or disable the TCC.
8.
Intel recommends the V
9.
This specification requires that the VID and BSEL signals be sampled no earlier than 10 μs after V
V
CC_BOOT
10. Parameter must be measured after applicable voltage level is stable. "Stable" means that the power supply
is in regulation as defined by the minimum and maximum DC/AC specifications for all components being
powered by it.
11. The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor.
Measured between (0.3* V
12. See
Table 2-19
Table 2-23. Front Side Bus AC Specifications (Reset Conditions)
T45: Reset Configuration Signals
(A[39:3]#, BR[1:0]#, INIT#, SMI#) Setup Time
T46: Reset Configuration Signals
(A[39:3]#, INIT#, SMI#) Hold Time
T47: Reset Configuration Signals
BR[1:0]# Hold Time
Notes:
1.
Before the clock that de-asserts RESET#
2.
After the clock that de-asserts RESET#.
Table 2-24. TAP Signal Group AC Specifications (Sheet 1 of 2)
T55: TCK Period
T56: TDI, TMS Setup Time
42
T# Parameter
removed
CC
stable to VID / BSEL valid
stable
CC
stable to PWRGOOD assertion
). PWRGOOD is referenced to BCLK0 rising edge at 0.5 * V
CROSS
Section 7.2
for additional timing requirements for entering and leaving low power states.
power supply also be removed upon assertion of THERMTRIP#.
TT
voltage) and V
are stable.
TT
) and (0.7*V
TT
for BCLK specifications.
T# Parameter
T# Parameter
Min
Max
30
1
10
10
500
500
0
5
0.05
500
20
10
100
10
1
Section 5
for more details information on behavior of the signal.
).
TT
Min
Max
480
2
20
2
2
Min
Max
30
7.5
Electrical Specifications
Notes
Unit
Figure
1, 2, 3, 4
ns
5
ms
2-24
BCLKs
2-24
6,12
µs
2-20
7
ms
2-21
8
BCLKs
2-25
ms
2-24
10
ns
11
µs
2-24
9,10
µs
2-24
10
µs
2-24
10
ms
2-24
10
.
TT
(at
CC
Unit
Figure
Notes
µs
2-24
1
BCLKs
2-24
2
BCLKs
2-24
2
Notes
Unit
Figure
1, 2, 8
ns
2-12
3
ns
2-19
4,7
Document Number: 318080-002
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