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Figure 6-8.
Conceptual Fan Control Diagram For a PECI-Based Platform
Fan Speed
Fan Speed
(RPM)
(RPM)
6.3.1.2
Processor Thermal Data Sample Rate and Filtering
The DTS (Digital Thermal Sensors) provide an improved capability to monitor device
hot spots, which inherently leads to more varying temperature readings over short
time intervals. The DTS sample interval range can be modified, and a data filtering
algorithm can be activated to help moderate this. The DTS sample interval range is 82
us (default) to 20 ms (max). This value can be set in BIOS.
To reduce the sample rate requirements on PECI and improve thermal data stability vs.
time the processor DTS also implements an averaging algorithm that filters the
incoming data. This is an alpha-beta filter with coefficients of 0.5, and is expressed
mathematically as: Current_filtered_temp = (Previous_filtered_temp / 2) +
(new_sensor_temp / 2). This filtering algorithm is fixed and cannot be changed. It is on
by default and can be turned off in BIOS.
Host controllers should utilize the min/max sample times to determine the appropriate
sample rate based on the controller's fan control algorithm and targeted response rate.
The key items to take into account when settling on a fan control algorithm are the DTS
sample rate, whether the temperature filter is enabled, how often the PECI host will
poll the processor for temperature data, and the rate at which fan speed is changed.
Depending on the designer's specific requirements the DTS sample rate and alpha-beta
filter may have no effect on the fan control algorithm.
6.3.2
PECI Specifications
6.3.2.1
PECI Device Address
The Intel
based on the processor APIC ID[4:2] at power on. APIC ID[4:3] is also known as
Cluster ID[1:0] and APIC ID[2] is also known as Agent ID[1]. Cluster ID[1:0] is set by
the chipset driven power-on configuration (POC) signals A[12:11]#.
how the Agent ID is generated for each of the die based on the BREQ# signals asserted
during power on for the Intel
108
Min
Min
(not intended to depict actual implementation)
(not intended to depict actual implementation)
®
®
Xeon
Processor 7200 Series and 7300 Series obtains its PECI address
®
Xeon
T
T
CONTROL
CONTROL
Setting
Setting
Max
Max
PECI = -10
PECI = -10
PECI = -20
PECI = -20
Temperature
Temperature
®
Processor 7200 Series and 7300 Series.
Thermal Specifications
TCC Activation
TCC Activation
Temperature
Temperature
PECI = 0
PECI = 0
Table 6-9
shows
Document Number: 318080-002
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