Figure 2-22. SMBus Timing Waveform
Clk
Data
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Figure 2-23. SMBus Valid Delay Timing Waveform
SM_CLK
SM_DAT
52
t
R
t
LOW
t HD;STA
t
HD;DAT
t BUF
S
START
t LOW
t HIGH =
t R
t F
TAA
TAA = T96
t
F
t
t
t
SU;STA
HIGH
SU;DAT
S
START
t HD;STA
t SU;STA =
=
T100
=
T93
t SU;STD =
t HD;DAT =
T98
T92
t BUF
=
T99
=
T94
t SU;DAT =
T97
=
T95
DATA VALID
DATA OUTPUT
Electrical Specifications
t HD;STA
t
SU;STO
T101
T102
Document Number: 318080-002
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