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Table 7-3.
Memory Device SMBus Addressing
Address
(Hex)
A0h/A1h
A2h/A3h
A4h/A5h
A6h/A7h
A8h/A9h
AAh/ABh
ACh/ADh
AEh/AFh
Note:
1.
This addressing scheme will support up to 8 processors on a single SMBus.
7.4.2
PIROM and Scratch EEPROM Supported SMBus
Transactions
The Processor Information ROM (PIROM) responds to two SMBus packet types: Read
Byte and Write Byte. However, since the PIROM is write-protected, it will acknowledge
a Write Byte command but ignore the data. The Scratch EEPROM responds to Read
Byte and Write Byte commands.
Table 7-5
ROM, software must allow a minimum of 10 ms before accessing either ROM of the
processor.
In the tables, 'S' represents the SMBus start bit, 'P' represents a stop bit, 'R' represents
a read bit, 'W' represents a write bit, 'A' represents an acknowledge (ACK), and '///'
represents a negative acknowledge (NACK). The shaded bits are transmitted by the
Processor Information ROM or Scratch EEPROM, and the bits that aren't shaded are
transmitted by the SMBus host controller. In the tables, the data addresses indicate 8
bits. The SMBus host controller should transmit 8 bits with the most significant bit
indicating which section of the EEPROM is to be addressed: the Processor Information
ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
Table 7-4.
Read Byte SMBus Packet
Slave
S
Addres
s
1
7-bits
Table 7-5.
Write Byte SMBus Packet
S
Slave Address
1
118
Upper
1
Address
SM_EP_A2
bits 7-4
bit 3
1010
0
1010
0
1010
0
1010
0
1010
1
1010
1
1010
1
1010
1
Table 7-4
diagrams the Write Byte command. Following a write cycle to the scratch
Comman
Write
A
d Code
1
1
8-bits
Write
7-bits
1
Device Select
SM_EP_A1
SM_EP_A0
bit 2
bit 1
0
0
1
1
0
0
1
1
diagrams the Read Byte command.
Slave
A
S
Read
Address
1
1
7-bits
1
A
Command Code
1
8-bits
Features
R/W
bit 0
0
X
1
X
0
X
1
X
0
X
1
X
0
X
1
X
A
Data
///
1
8-bits
1
A
Data
A
1
8-bits
1
Document Number: 318080-002
P
1
P
1
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