Tap Valid Delay Timing Waveform; Test Reset (Trst#), Async Gtl+ Input, And Prochot# Timing Waveform; Thermtrip# Power Down Sequence - Intel BFCBASE - Motherboard - 7300 Datasheet

Electrical Specifications
Figure 2-19. TAP Valid Delay Timing Waveform
Note: Please refer to
AC specifications.
Figure 2-20. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform
T
q
Figure 2-21. THERMTRIP# Power Down Sequence
Document Number: 318080-002
V
TCK
Tx
Signal
Tx = T58: TDO Clock to Output Delay
Ts = T56: TDI, TMS Setup Time
Th = T57: TDI, TMS Hold Time
V = 0.5 * V
Table 2-12 for TAP Signal Group DC specifications and
V
T59 (TRST# Pulse Width), V = 0.5 * V
=
T38 (PROCHOT# Pulse Width), V = GTLREF
THERMTRIP#
Vcc
V
TT
T = T39 (THERMTRIP# to removal of power)
A
Ts Th
V Valid
TT
T
q
TT
T
A
Table 2-24 for TAP Signal Group
51