Omron CQM1H - PROGRAM Programming Manual page 96

High-speed Counter Board
Reset Methods
Checking Methods for
High-speed Counter
Interrupts
The following two methods can be set to determine the timing at which the PV
of the counter is reset (i.e., set to 0):
• Phase-Z signal + software reset
• Software reset
Phase-Z Signal (Reset Input) + Software Reset
The PV of the high-speed counter is reset in the first rising edge of the phase-
Z signal after the corresponding High-speed Counter Reset Bit (see below)
turns ON.
Phase-Z
(reset input)
High-speed Counter
Reset Bit
Software Reset
The PV is reset when the High-speed Counter Reset Bit turns ON. There are
separate Reset Bits for each high-speed counter 1 to 4.
The Reset Bits of high-speed counters 1 to 4 are given in the following table.
Counter
High-speed counter 1
High-speed counter 2
High-speed counter 3
High-speed counter 4
Reset Bits for high-speed counters 1 to 4 are refreshed only once each cycle.
A Reset Bit must be ON for a minimum of 1 cycle to be read reliably.
Note The comparison table registration and comparison execution status will not be
changed when the PV is reset. If a comparison was being executed before the
reset, it will continue.
The following two methods are available to check the PV of high-speed
counters 1 to 4. (These are the same methods as those used for built-in high-
speed counter 0.)
• Target value method
• Range comparison method
Refer to page 36 for a description of each method.
For the target value method, a maximum of 48 target values can be registered
in the comparison table. When the PV of the counter matches one of the 48
1 or more cycles Within 1 cycle
Reset by interrupt.
1 or more cycles
High-speed Counter
Reset Bit
Within 1 cycle
Reset by cycle.
Slot 1
IR 21200
IR 21201
IR 21202
IR 21203
Section 2-1
1 or more cycles
Reset by cycle. Not reset.
Reset Bit
Slot 2
AR 0500
AR 0501
AR 0502
AR 0503
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