Omron CQM1H - PROGRAM Programming Manual page 52

Interrupt Functions
Input Interrupt Mode
Counter Mode
1,2,3...
routine for input interrupt 0 unless it was refreshed (in this case, the Always
ON Flag, SR 25313 could be used in place of IR 00000).
Use the following instructions to program input interrupts using the Input Inter-
rupt Mode.
Masking of Interrupts
With the INT(89) instruction, set or clear input interrupt masks as required.
(@)INT(89)
At the beginning of operation, all of the input interrupts are masked. Use
INT(89) to unmask input interrupts before using input interrupts in input inter-
rupt mode.
Clearing Masked Interrupts
If the bit corresponding to an input interrupt turns ON while masked, that input
interrupt will be saved in memory and will be executed as soon as the mask is
cleared. In order for that input interrupt not to be executed when the mask is
cleared, the interrupt must be cleared from memory.
Only one interrupt signal will be saved in memory for each interrupt number.
With the INT(89) instruction, clear the input interrupt from memory.
(@)INT(89)
001
000
Reading Mask Status
With the INT(89) instruction, read the input interrupt mask status.
(@)INT(89)
002
000
D
Use the following steps to program input interrupts using the Input Interrupt
Mode.
Note The SR words used in the Counter Mode (SR 244 to SR 251) all contain
binary (hexadecimal) data (not BCD).
1. Write the set values for counter operation to SR words correspond to inter-
rupts 0 to 3. The set values are written between 0000 and FFFF (0 to
65,535). A value of 0000 will disable the count operation until a new value
is set and step 2, below, is repeated.
Note These SR bits are cleared at the beginning of operation, and must be
written from the program.
That maximum input signal that can be counted is 1 kHz.
Interrupt
Input interrupt 0
Input interrupt 1
Input interrupt 2
Input interrupt 3
Make the settings with the D bits 0 to 3, which correspond to
input interrupts 0 to 3.
000
0: Mask cleared. (Input interrupt permitted.)
000
1: Mask set. (Input interrupt not permitted.)
D
If D bits 0 to 3, which correspond to input interrupts 0 to 3, are
set to "1," then the input interrupts will be cleared from memory.
0: Input interrupt retained.
1: Input interrupt cleared.
D
The status of the rightmost digit of the data stored in word D (bits
0 to 3) show the mask status.
0: Mask cleared. (Input interrupt permitted.)
1: Mask set. (Input interrupt not permitted.)
Word containing counter SV
SR 244
SR 245
SR 246
SR 247
Section 1-4
27