Interrupt Processing Time - Omron CQM1H - PROGRAM Programming Manual

Cycle Time
7-3-5

Interrupt Processing Time

Processing Time
Item
Interrupt input ON delay
Standby until completion
of interrupt-mask pro-
cessing
Change-to-interrupt pro-
cessing
Input refresh at time of
interrupt
Return
Note
The maximum I/O response time is as follows:
Input ON delay:
Master cycle time:
Transmission time:
Slave cycle time:
+ Output ON delay:
Maximum I/O response time:
This section explains the processing times involved from the time an interrupt
is executed until the interrupt processing routine is called, and from the time
an interrupt processing routine is completed until returning to the original posi-
tion. The explanation applies to the following three types of interrupts: input
interrupts, interval timer interrupts, and high-speed counter interrupts.
The table below shows the times involved from the generation of an interrupt
signal until the interrupt processing routine is called, and from when the inter-
rupt processing routine is completed until returning to the original position.
This is the delay time from the time the interrupt input bit turns ON
until the time that the interrupt is executed. This is unrelated to
other interrupts.
↓ (Interrupt condition realized.) (see note)
This is the time during which interrupts are waiting until processing
has been completed. This situation occurs when a mask pro-
cesses is executed. It is explained below in more detail.
This is the time it takes to change processing to an interrupt.
This is the time required for input refresh when input refresh is set
to be executed at the time the interrupt processing routine is
called. (Set in PC Setup, DM 6630 to DM 6638.)
↓ (Interrupt processing routine executed)
This is the time it takes, from execution of RET(93), to return to the
processing that was interrupted.
1. When high-speed counter 0 is used with a range comparison table, the tim-
ing of interrupt processing can be affected by the cycle time.
2. When high-speed counters 1 and 2 for Pulse I/O Boards or Absolute En-
coder Interface Boards are used with range comparison tables (with
CQM1H-51/61 CPU Units), the timing of interrupt processing can be de-
layed up to 1 ms.
Mask Processing
Interrupts are masked during processing of the operations described below.
Until the processing is completed, any interrupts will remain masked for the
indicated times.
8 ms
10 ms × 2
39 ms × 3
15 ms × 2
10 ms
185 ms
Contents
↓
↓
Section 7-3
Time
50 µs
See below.
Input interrupts, internal
timer interrupts, or high-
speed counter interrupts:
30 µs
Interrupts from Serial
Communications Board:
55 µs
10 µs per word
30 µs
495