High-Speed Timers - Omron CQM1H - PROGRAM Programming Manual

Basic PC Operation and I/O Processes
1-3-7

High-speed Timers

Note
Input Time Constants for IR 000 and IR 001
Time constant for IR 00100 to IR 00115 (1-digit BCD; see below.)
Time constant for IR 00008 to IR 00015 (1 digit BCD; see below.)
Time constant for IR 00000 to IR 00007 (1 digit BCD; see below.)
Default: 0000 (8 ms for each)
Input Time Constants for IR 002 to IR 015
DM 6621: IR 002 and IR 003
DM 6622: IR 004 and IR 005
DM 6623: IR 006 and IR 007
DM 6624: IR 008 and IR 009
DM 6625: IR 010 and IR 011
DM 6626: IR 012 and IR 013
DM 6627: IR 014 and IR 015
Time constant for IR 003, IR 005, IR 007, IR 009, IR 011, IR 013, and IR 015
Time constant for IR 002, IR 004, IR 006, IR 008, IR 010, IR 012, and IR 014
Default: 0000 (8 ms for each)
The nine possible settings for the input time constant are shown below. Set
only the rightmost digit for IR 000.
0: 8 ms 1: 1 ms
5: 16 ms 6: 32 ms
Make the settings shown below to set the number of high-speed timers cre-
ated with TIMH(15) that will use interrupt processing.
High-speed timer interrupt setting enable
00: Setting disabled (Interrupt processing for all high-speed timers, TIM 000 to TIM 015)
01: Enabled (Use setting in bits 00 to 07.)
Number of high-speed timer for interrupts (valid when bits 08 to 15 are 01)
00 to 15 (2-digit BCD)
Default: Interrupt processing for all high-speed timers,TIM 000 to TIM 015.
The setting indicates the number of timers that will use interrupt processing
beginning with TIM 000. For example, if "0108" is specified, then eight timers,
TIM 000 to TIM 007 will use interrupt processing.
1. High-speed timers will not be accurate without interrupt processing unless
the cycle time is 10 ms or less.
2. If the SPED(64) instruction is used and pulses are output at a frequency of
500 Hz or greater, then set the number of high-speed timers with interrupt
processing to four or less. Refer to information on the SPED(64) instruction
for details.
3. Interrupt response time for other interrupts will be improved if interrupt pro-
cessing is set to 00 when high-speed timer processing is not required. This
includes any time the cycle time is less than 10 ms.
Bit
DM 6620
DM 6621 to DM 6627
2: 2 ms 3: 4 ms
7: 64 ms 8: 128 ms
DM 6629
Section 1-3
15 0
0
15 0
Bit
4: 8 ms
15 0
Bit
15