Page 1 Cat. No. W228-E1-08 SYSMAC CQM1/CPM1/CPM1A/SRM1 Programmable Controllers PROGRAMMING MANUAL...
Page 2 CQM1/CPM1/CPM1A/SRM1 Programmable Controllers Programming Manual Revised December 2005...
Page 4 1. Indicates lists of one sort or another, such as procedures, checklists, etc. OMRON, 1993 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form, or by any means, mechanical, electronic, photocopying, recording, or otherwise, without the prior written permission of OMRON.
Page 6: Table Of Contents
Basic PC Operation and I/O Processes ........
Page 7 Instruction Format ..........Data Areas, Definer Values, and Flags ....... . .
Page 8 Error and Arithmetic Flag Operation ........
Page 10 Section 3 describes the structure of the PC’s memory areas, and explains how to use them. It also describes Memory Cassette operations used to transfer data between the CQM1 and a Memory Cas- sette.
Page 12 Conformance to EC Directives ........
Page 13: Intended Audience
!WARNING It is extremely important that a PC and all PC Units be used for the specified purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PC System to the above-mentioned applica- tions.
Page 14: Operating Environment Precautions
!Caution When connecting the PC to a personal computer or other peripheral device, either ground the 0-V side of the PC or do not ground the PC at all. Although some grounding methods short the 24-V side, as shown in the following dia- gram, never do so with the PC.
Page 15: Application Precautions
Insufficient safety measures against short-cir- cuiting may result in burning. • Do not apply voltages to the Input Units in excess of the rated input volt- age. Excess voltages may result in burning. • Do not apply voltages or connect loads to the Output Units in excess of the maximum switching capacity.
Page 16 DM and HR Areas required for resuming operation. Not doing so may result in an unexpected operation. • Do not place objects on top of the cables. Doing so may break the cables. • Before touching the Unit, be sure to first touch a grounded metallic object in order to discharge any static built-up.
Page 17 ON unless it is turned OFF using I/O monitor operations, using memory clear operations, or from the user program. If desired, the PC Setup setting in DM 6604 can be set to create a fatal error and thus stop the system when AR 1314 goes ON.
Page 18: Conformance To Ec Directives
OFF for a period exceeding the data backup period of the internal lithium bat- tery. If the AR 1414 flag is ON, the data will be held unless it is turned OFF using the I/O Monitor operation, instructions, etc. The system can be stopped...
Page 19 If the supply voltage is 100 to 200 V, insert the varistor between the con- tacts. When switching a load with a high inrush current, such as an incandescent lamp, suppress the inrush current as shown below.
Page 20 Conformance to EC Directives Countermeasure 1 Countermeasure 2 Providing a dark current of approx. Providing a limiting resistor one-third of the rated value through an incandescent lamp...
Page 21 Conformance to EC Directives xxii...
Page 22: Pc Setup And Other Features
1-2-7 Input Time Constants ........
Page 23 Types of Interrupts........
Page 24: Pc Setup
DM 6615 to DM 6644 effective. When DM 6602 bits 00 to 03 are set to protect the program memory, DM 6602 cannot be changed using the PC Setup operation of the Support Software. To change DM 6602, use the I/O Monitor or DM Edit operation.
Page 25: Cqm1 Pc Setup Settings
Function Page Startup Processing (DM 6600 to DM 6614) The following settings are effective after transfer to the PC only after the PC is restarted. DM 6600 00 to 07 Startup mode (effective when bits 08 to 15 are set to 02).
Page 26 00 to 03 Input constant for IR 00000 to IR 00007 0: 8 ms; 1: 1 ms; 2: 2 ms; 3: 4 ms; 4: 8 ms; 5: 16 ms; 6: 32 ms; 7: 64 ms; 8: 128 ms 04 to 07...
Page 27 Number of input refresh words for interval timer 1: 00 to 08 (BCD) DM 6638 00 to 07 First input refresh word for interval timer 2 (also used for high-speed counter 0): 00 to 07 (BCD) 08 to 15 Number of input refresh words for interval timer 2: 00 to 08 (BCD)
Page 28 08 to 11 Link words for 1:1 link (Effective when bits 12 to 15 are set to 3.) 0: LR 00 to LR 63; 1: LR 00 to LR 31; 2: LR 00 to LR 15 12 to 15 Communications mode 0: Host link;...
Page 29 0000 to 9999: In ms. DM 6653 00 to 07 Node number (Host link, effective when bits 12 to 15 of DM 6650 are set to 0.) 00 to 31 (BCD) 08 to 11 Start code enable (RS-232C, effective when bits 12 to 15 of DM 6650 are set to 1.) 0: Disable;...
Page 30: Cpm1/Cpm1A Pc Setup Settings
DM 6604 00 to 07 00: If data could not be saved with the built-in capacitor (AR 1314 ON), a memory error will not be generated. 01: If data could not be saved with the built-in capacitor (AR 1314 ON), a memory error will be generated.
Page 31 00 to 03 Input constant for IR 00000 to IR 00002 0: 8 ms; 1: 1 ms; 2: 2 ms; 3: 4 ms; 4: 8 ms; 5: 16 ms; 6: 32 ms; 7: 64 ms; 8: 128 ms 04 to 07...
Page 32 00 to 07 Baud rate 00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.2K, 05 to 07: Cannot be used (see note 2) (Other settings will cause a non-fatal error and AR 1302 will turn ON.) 08 to 15...
Page 33 PC Setup Section 1-1 2. Do not set to “05” to “07.” If set to this value, the CPM1/CPM1A will not op- erate properly and the RUN PC Setup Error Flag (AR 1302 ON) will not turn ON. 3. Retention of IOM Hold Bit (SR 25212) Status If the “IOM Hold Bit Status at Startup”...
Page 34: Srm1 Pc Setup Settings
DM 6604 00 to 07 00: If data could not be saved for a power interruption (AR 1314 ON), a memory error will not be generated. 01: If data could not be saved for a power interruption (AR 1314 ON), a memory error will be generated.
Page 35 Link words for 1:1 link 0: LR 00 to LR 15; Other: Not effective 12 to 15 Communications mode 0: Host link; 1: RS-232C (no protocol); 2: 1:1 data link slave; 3: 1:1 data link master; 4: NT Link DM 6646 00 to 07 Baud rate 00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.2K...
Page 36 00 to 31 (BCD) (Other settings will cause a non-fatal error and AR 1302 will turn ON.) 08 to 11 Start code enable (RS-232C, effective when bits 12 to 15 of DM6650 are set to 1.) 0: Disable 1: Set 12 to 15 End code enable (RS-232C, effective when bits 12 to 15 of DM6650 are set to 1.)
Page 37: Basic Pc Operation And I/O Processes
This section explains the PC Setup settings related to basic operation and I/O processes. 1-2-1 Startup Mode The operation mode the PC will start in when power is turned on can be set as shown below. DM6600 Startup Mode Designation...
Page 38: Hold Bit Status
!Caution Do not use the I/O Hold Bit Status and Forced Status Hold Bit Status Bits (DM 6601) when the power to the PC is going to be turned off longer than the memory backup time of the internal capacitor. If the memory backup time is exceeded, memory status will be unstable even if the I/O Hold Bit Status and Forced Status Hold Bit Status Bits are used.
Page 39: Rs-232C Port Servicing Time (Cqm1/Srm1 Only)
Servicing time (%, valid with bits 08 to 15 are 01) 00 to 99 (BCD, two digits) Default: 5% of cycle time Example: If DM 6616 is set to 0110, the RS-232C port will be serviced for 10% of the cycle time. The servicing time will be 0.34 ms minimum.
Page 40: Input Time Constants
DM 6627: IR 014 and IR 015 Time constant for IR 003, IR 005, IR 007, IR 009, IR 011, IR 013, and IR 015 Time constant for IR 002, IR 004, IR 006, IR 008, IR 010, IR 012, and IR 014 Default: 0000 (8 ms for each) The nine possible settings for the input time constant are shown below.
Page 41: High-Speed Timers (Cqm1 Only)
DM 6625: IR 009 Time constant for IR 002, IR 004, IR 006, and IR 008 Time constant for IR 001, IR 003, IR 005, IR 007, and IR 009 Default: 0000 (8 ms for each) The nine possible settings for the input time constant are shown below. Set only the rightmost digit for IR 000.
Page 42: Dsw(87) Input Digits & Output Refresh Method (Cqm1 Only)
1. The unit used for the maximum and current cycle times recorded in the AR area (AR 26 and AR 27 in the CQM1, AR 14 and AR 15 in the CPM1/ CPM1A/SRM1) depend on the unit set for the cycle monitor time in DM 6618, as shown below.
Page 43: Pulse Output Function (Cqm1 Only)
AR area. Example If 0230 is set in DM 6618, an FALS 9F error will not occur until the cycle time exceeds 3 s. If the actual cycle time is 2.59 s, the current cycle time stored in the AR area will be 2590 (ms), but the cycle time read from a Programming Device will be 999.9 ms.
Page 44: Standard Pulse Output From An Output Point
With the CQM1-CPU43-EV1, standard pulses (duty ratio = 50%) can be out- from Ports 1 and 2 put from port 1 and/or 2 with a frequency from 10 Hz to 50 kHz (20 kHz max. to a stepping motor). The pulse output can be either clockwise (CW) or counter-clockwise (CCW) and frequency changes can be made smoothly.
Page 45 Pulse Output Function (CQM1 Only) Section 1-3 2. The total number of pulses that will be output can be set with PULS(65) be- fore execution of SPED(64). In this case, SPED(64) must be executed in independent mode. The pulse output stops automatically when the num- ber of pulses set by PULS(65) have been output.
Page 46: Standard Pulse Output From Ports 1 And 2
With the CQM1-CPU43-EV1, standard pulses can be output from ports 1 and 2 using SPED(64), PLS2(––), or ACC(––). The pulse frequency can be set from 10 Hz to 50 kHz (20 kHz max. to a stepping motor). The pulse output can be either clockwise (CW) or counter-clockwise (CCW) and frequency changes can be made smoothly.
Page 47 Section 1-3 Pulse Output Function (CQM1 Only) 2. The total number of pulses that will be output can be set with PULS(65) be- fore execution of SPED(64). In this case, SPED(64) must be executed in independent mode. The pulse output stops automatically when the num- ber of pulses set by PULS(65) have been output.
Page 48 CTBL(63) cannot be used with ports 1 and 2. The setting in DM 6611 is read only when the CQM1 is started. If this setting is changed, be sure to turn the PC off and then on again to make the new set- ting effective.
Page 49 Section 1-3 Pulse Output Function (CQM1 Only) The following diagram shows the frequency of pulse outputs from port 1 as the program is executed. Frequency 1.5 kHz 1.0 kHz 0.5 kHz Time 05000 00000 00001 00002 10,000 goes ON goes ON...
Page 50 Example 3: PLS2(– –) The following example shows PLS2(––) used to output 100,000 CW pulses from port 1. The frequency is accelerated to 10 kHz at approximately 500 Hz/ 4 ms and decelerated at the same rate. Five seconds after the CW pulses have been output, another PLS2(––) instruction outputs 100,000 CCW pulses with the same settings.
Page 51 Example 5: ACC(––) The following example shows mode 1 of ACC(––) used increase the fre- Mode 1 quency of a pulse output from port 1. The frequency is accelerated from 1 kHz to 20 kHz at approximately 500 Hz/4 ms. DM 0000...
Page 52 The following example shows mode 2 of ACC(––) used decrease the fre- Mode 2 quency of a pulse output from port 1. The 2-kHz pulse output is already in progress in independent mode and stops automatically when the number of pulses is reached.
Page 53: Variable-Duty-Ratio Pulse Output From Ports 1 And 2
Pulses will begin to be output from the specified port when PWM(––) is exe- cuted. Specify port 1 or 2 (P=001 to 002). Set the frequency to 5.9 kHz, 1.5 kHz, or 91.6 Hz (F=000, 001, or 002). Set the duty ratio from 1% to 99% (D=0001 to 0099, BCD).
Page 54 Example: Using PWM(––) The following example shows PWM(––) used to start a 1.5 kHz pulse output from port 1 and change the duty ratio from 50% to 25%.The pulse output is then stopped with INI(61). Before executing the program make sure that DM 6643 is set to 1000 (vari- able-duty-ratio pulse setting for port 1).
Page 55: Determining The Status Of Ports 1 And 2
1 or 2 (P=001 to 002) and the destination word D. The port status infor- mation will be written to bits 04 to 07 of D and bits 00 to 03 and 08 to 15 will be set to 0.
Page 56: Pulse Output Function (Cpm1A Only)
20 Hz to 2 kHz (single-phase). Either IR 01000 or IR 01001 can be selected for pulse output, and the pulse output can be set to either the continuous mode, under which the output can be stopped by an instruction, or the independent mode, under which the output is stopped after a preset number of pulses (1 to 16,777,215).
Page 57: Programming Example In Continuous Mode
In N, set the beginning word address of the words where the number of pulses is set. Store the number of pulses in words N and N+1, in eight digits BCD, with the leftmost four digits in N+1 and the rightmost four digits in N.
Page 58: Changing The Frequency
1. Use SPED(64) to set the frequency to 0. 2. Use INI(61) to stop the pulse output. Using SPED(64) The first method is to use SPED(64) to stop the pulse output by setting the frequency to 0. For details, refer to 1-4-4 Changing the Frequency. Using INI(61)
Page 59: Cqm1 Interrupt Functions
0 has the lowest.) 1,2,3... 1. Input interrupt 0 > Input interrupt 1 > Input interrupt 2 > Input interrupt 3 2. High-speed counter interrupt 1 > High-speed counter interrupt 2 3. Interval timer interrupt 0 > Interval timer interrupt 1 > Interval timer interrupt 2 (Interval timer interrupt 2 is high-speed counter interrupt 0.)
Page 60 CQM1 Interrupt Functions INI(61), PRV(62), CTBL(63), SPED(64), PULS(65), PWM(––), PLS2(––) and ACC(––) The following methods can be used to circumvent this limitation: Method 1 All interrupt processing can be masked while the instruction is being exe- cuted. @INT(89) @PLS2(––) DM 0010...
Page 61: Input Interrupts
00 to 07 Default: No input refresh Example: If DM 6630 is set to 0100, IR 000 will be refreshed when a signal is received for interrupt 0. Note If input refreshing is not used, input signal status within the interrupt routine will not be reliable.
Page 62 If the bit corresponding to an input interrupt turns ON while masked, that input interrupt will be saved in memory and will be executed as soon as the mask is cleared. In order for that input interrupt not to be executed when the mask is cleared, the interrupt must be cleared from memory.
Page 63 Example: The present value for an interrupt whose set value is 000A will be recorded as 0009 immediately after INT(89) is executed. Note Even if input interrupts are not used in Counter Mode, these SR bits cannot be used as work bits.
Page 64 Section 1-5 CQM1 Interrupt Functions Application Example In this example, input interrupt 0 is used in Input Interrupt Mode and input interrupt 1 is used in Counter Mode. Before executing the program, check to be sure the PC Setup. PC Setup: DM 6628: 0011 (IR 00000 and IR 00001 used for input interrupts) The default settings are used for all other PC Setup parameters.
Page 65: Masking All Interrupts
INT(89) instruction. The mask is in addition to any masks on the individ- ual types of interrupts. Furthermore, clearing the masks for all interrupts does...
Page 66: Interval Timer Interrupts
+ 1) x 0.1 ms = (0.5 to 319,968 ms) If a constant is set for C , then the set value of the decrementing counter will take that value and the decrementing time interval will be 10 (1 ms). (The set value is expressed in ms.)
Page 67 The time from when the interval timer is started until the execution of this instruction is calculated as follows: {(Contents of word C2) x (Contents of word C2 + 1) + (Contents of word C3)} x 0.1 ms If the specified interval timer is stopped, then “0000” will be stored.
Page 68: High-Speed Counter 0 Interrupts
Section 1-5 Application Example In this example, an interrupt is executed every 2.4 ms (0.6 ms x 4) by means of interval timer 1. Assume the default settings for all of the PC Setup. (Inputs are not refreshed for interrupt processing.)
Page 69 Reset by cycle. Not reset. Reset by cycle. Note The High-speed Counter 0 Reset Bit (SR 25200) is refreshed once every cycle, so in order for it to be read reliably it must be ON for at least one cycle.
Page 70 Once the count has equaled all of the target values in the table, the target value is set to the first target value in the table, which is again compared to the current counted until the two values are equal.
Page 71 Pulse count input Encoder B-phase Encoder Z-phase Reset input If only the software reset is to be used, terminal 6 can be used as an ordinary input. When in Incrementing Mode, terminal 5 can be used as an ordinary input. PC Setup When using high-speed counter 0 interrupts, make the settings in PROGRAM mode shown below before executing the program.
Page 72 (i.e., during program execution) as long as no other table is saved. Reading the PV There are two ways to read the PV. The first is to read it from SR 230 and SR 231, and the second to use the PRV(62) instruction.
Page 73 There are two ways to change the PV of high-speed counter 0. The first way is to reset it by using the reset methods. (In this case the PV is reset to 0.) The second way is to use the INI(61) instruction.
Page 74: High-Speed Counter 0 Overflows/Underflows
Begins continuous pulse output to IR10002 at 500 Hz. #0050 SBN(92) 25313 (Always ON) SPED(64) When the high-speed counter value reaches 1000, subroutine 101 is called and the frequency of the pulse output is changed to 200 Hz. #0020 RET(93) SBN(92) 25313 (Always ON)
Page 75 The values will actually be those that existed one cycle before the overflow/underflow existed. 2. The 6th and 7th digits of high-speed counter 0’s PV are normally 00, but can be used as “Overflow/Underflow Flags” by detecting values beyond the allowable counting ranges.
Page 76: High-Speed Counter 1 And 2 Interrupts (Cqm1-Cpu43-Ev1)
CTBL(63) cannot be used with ports 1 and 2. Processing Input Signals and Count Modes Three types of signals can be input to ports 1 and 2. The count modes used for high-speed counters 1 and 2 are set in DM 6643 and DM 6644 respec- tively.
Page 77 PV will remain at 0838 8607 for overflows and F838 8607 for underflows, counting or com- parison will be stopped, and AR 0509 (port 1) or AR 0609 (port 2) will be turned ON.
Page 78 Section 1-5 CQM1 Interrupt Functions This setting is read when the PC is turned ON. If it is changed, the PC must be turned off and then on again before executing the program. DM 6611 Port 1 and 2 Mode Setting 0000: High-speed counter mode Default: The default mode setting is high-speed counter mode.
Page 79 (i.e., during program execution) as long as no other table is saved. Reading the PV There are two ways to read the PV. The first is to read it from SR 232 and SR 233 (port 1) or SR 234 and SR 235 (port 2), and the second is to use PRV(62).
Page 80 There are two ways to change the PV of high-speed counters 1 and 2. The first way is to reset it by using the reset methods. (In this case the PV is reset to 0.) The second way is to use the INI(61) instruction.
Page 81 The status of high-speed counters 1 and 2 can also be determined by execut- ing PRV(62). Specify high-speed counter 1 or 2 (P=001 to 002) and the desti- nation word D. The status information will be written to bits 00 and 01 of D. Bits 02 to 15 will be set to 0.
Page 82 Section 1-5 CQM1 Interrupt Functions In addition, the following data is stored for the comparison table: DM 0000 0003 Number of comparison conditions: 3 DM 0001 2500 Target value 1: 2,500 DM 0002 0000 DM 0003 0100 Comparison 1 interrupt processing routine no.: 100...
Page 83: Absolute High-Speed Counter Interrupts (Cqm1-Cpu44-Ev1)
2 of the CQM1-CPU44-EV1 and counted at 4 kHz. Interrupt processing can be executed according to the count. The 2 ports can be operated separately. The counter for port 1 is called abso- lute high-speed counter 1 and the counter for port 2 is called absolute high- speed counter 2.
Page 84 1. Set the absolute rotary encoder to the desired origin location. 2. Make sure that pin 1 of the CPU Unit’s DIP switch is OFF (enabling Periph- eral Devices to overwrite DM 6614 through DM 6655) and switch the PC to PROGRAM mode.
Page 85 Reading the PV There are two ways to read the PV. The first is to read it from IR 232 and IR 233 (port 1) or IR 234 and IR 235 (port 2), and the second is to use PRV(62).
Page 86 PRV(62). Specify absolute high-speed counter 1 or 2 (P=001 to 002) and the destination word D. The flag status (0: Stopped; 1: Comparing) will be written to bit 00 of D. Bits 01 to 15 will be set to 0. Execution condition...
Page 87: Mov(21)
Section 1-5 CQM1 Interrupt Functions DM 0000 0000 Lower limit #1 (0 ) First range setting (0 to 85 ) DM 0001 0085 Upper limit #1 (85 ) DM 0002 0100 Subroutine number 100 DM 0003 0090 Lower limit #2 (90 )
Page 88: Cpm1/Cpm1A Interrupt Functions
When two interrupts with equal priority are received at the same time, they are executed in the following order: Input interrupt 0 > Input interrupt 1 > Input interrupt 2 > Input interrupt 3 Interval interrupts > High-speed counter interrupts...
Page 89 Section 1-6 CPM1/CPM1A Interrupt Functions 4. An interrupt program cannot be written within a subroutine program. Do not write an interrupt program between a SUBROUTINE DEFINE instruction (SBN(92)) and a RETURN instruction (RET(93)). Inputs used as interrupts cannot be used as regular inputs.
Page 90: Input Interrupts
25313 0000 Note 1. Define interrupt routines at the end of the main program with SBN(92) and RET(93) instructions, just like regular subroutines. 2. When defining an interrupt routine, a “SBS UNDEFD” error will occur dur- ing the program check operation, but the program will be executed normal-...
Page 91 CPM1/CPM1A. Set the corresponding digit to 1 if the input is to be used as an interrupt input (input interrupt or counter mode); set it to 0 if it is to be used as a regular input.
Page 92 Section 1-6 For example, IR 00000 would not be ON in interrupt routine for input interrupt 0 unless it was refreshed. In this case, use the Always ON Flag, SR 25313 in the interrupt routine instead of IR 00000. Input Interrupt Mode...
Page 93 Use the following steps to program input interrupts using the Counter Mode. 1,2,3... 1. Write the set values for counter operation to the SR words shown in the fol- lowing table. The set values are written between 0000 and FFFF (0 to 65,535).
Page 94 0: Counter mode set value refreshed and mask cleared. 1: Not refreshed. Be sure to set the corresponding bit to 1 if an input interrupt isn’t being con- trolled. The input interrupt for which the set value is refreshed will be enabled in Counter Mode.
Page 95: Masking All Interrupts
INT(89) instruction. The mask is in addition to any masks on the individ- ual types of interrupts. Furthermore, clearing the masks for all interrupts does...
Page 96: Interval Timer Interrupts
Sched- uled Interrupt Mode in which the interrupt is repeated at a fixed interval. The interval timer’s set value can be set anywhere from 0.5 to 319968 ms, in units of 0.1 ms.
Page 97 2. When C is entered as a constant: The settings are the same as for the one-shot mode, but interrupts will con- tinue to be repeated at fixed intervals until the operation is stopped. Reading the Timer’s Elapsed Time Use the STIM(69) instruction to read the timer’s elapsed time.
Page 98: High-Speed Counter Interrupts
Specifies the subroutine number (23). SBN(92) Interrupt program RET(93) Application Example In this example, an interrupt is generated every 4.0 ms (1.0 ms 4) after input (Scheduled Interrupt 00005 goes ON; the interrupts execute interrupt subroutine number 23. Mode) 25315 First Cycle Flag...
Page 99 Note In incrementing mode, input 00001 can be used as a regular input. When the reset method is used for the software reset, input 00002 can be used as a regular input. Also, even when used for the Z-phase signal and software reset, the input status is reflected inn 00002 of the I/O memory.
Page 100 Incrementing Mode Pulse input A-phase B-phase Count 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 –1 –2 Count Incremented Decremented Incremented only Note One of the reset methods described below should always be used to reset the counter when restarting it.
Page 101 Note The High-speed Counter Reset Bit (SR 25200) is refreshed once every cycle, so in order for it to be read reliably it must be ON for at least one cycle. The “Z” in “Z-phase” is an abbreviation for “Zero.” It is a signal that shows that the encoder has completed one cycle.
Page 102 Once the count has equaled all of the target values in the table, the target value is set to the first target value in the table, which is again compared to the current counted until the two values are equal.
Page 103 (i.e., during program execution) as long as no other table is saved. Reading the PV There are two ways to read the PV. The first is to read it from SR 248 and SR 249, and the second to use the PRV(62) instruction. Reading SR 248 and SR 249 The PV of high-speed counter is stored in SR 248 and SR 249 as shown below.
Page 104 There are two ways to change the PV of high-speed counter. The first way is to reset it by using the reset methods. (In this case the PV is reset to 0.) The second way is to use the INI(61) instruction.
Page 105 Section 1-6 CPM1/CPM1A Interrupt Functions The following diagram shows the example ladder program. DM 6642 must be set to 01@4, where @ is the reset method which can be set to 0 or 1. 25315 (ON for first cycle) CTBL(63)
Page 106: Srm1 Interrupt Functions
Range 8 interrupt subroutine not executed The following diagram shows the example ladder program. DM 6642 must be set to 01@0, where @ is the reset method which can be set to 0 or 1. 25315 (ON for first cycle)
Page 107 The meanings of the settings are the same as for the one-shot mode, but in the scheduled interrupt mode the timer PV will be reset to the set value and decrementing will begin again after the subroutine has been called. In the scheduled interrupt mode, interrupts will continue to be repeated at fixed intervals until the operation is stopped.
Page 108 Section 1-7 SRM1 Interrupt Functions If the specified interval timer is stopped, then “0000” will be stored. Stopping the Timer Use the STIM(69) instruction to stop the interval timer. The interval timer will be stopped. (@)STIM(69) : Stop interval timer (010) Application Example In this example, an interrupt is generated 2.4 ms (0.6 ms...
Page 109: Compobus/S Distributed I/O Functions (Srm1 Only)
Slave Interrupts Input bits in IR 000 to IR 007 and output bits in IR 010 to IR 017 are used as interrupts for CompoBus/S I/O Terminals. The CompoBus/S I/O Terminal interrupts (IN 0 to 15 and OUT 0 to 15) are allocated as indicated in the follow- ing table.
Page 110: Communications Functions
IN11 IN10 Note 1. IN0 to IN15 are the input terminals and OUT0 to OUT15 are the output ter- minals. 2. When the maximum number of CompoBus/S units is set to 16, IN8 to IN15 and OUT8 to OUT15 cannot be used.
Page 111: Cqm1 Pc Setup
Host Link Communications in the CPM1A Operation Manual for more details. 1-to-1 Link A data link can be created with a data area in another CPM1, CPM1A, CQM1, or C200HS PC. An RS-232C Adapter is used to make the 1-to-1 connection.
Page 112 Note The above setting apply to CPU Units manufactured from July 1995 (lot num- ber **75 for July 1995). For CPU Units manufactured before July 1995 (lot number **65 for June 1995), only 1 stop bit will be set and the baud rate will be 2,400 bps.
Page 113 Specify whether or not a start code is to be set at the beginning of the data, and whether or not an end code is to be set at the end. Instead of setting the end code, it is possible to specify the number of bytes to be received before the reception operation is completed.
Page 114: Wiring Ports
PCs and one or more host computers by RS-232C cable, and control- ling PC communications from the host computer. Normally the host computer issues a command to a PC, and the PC automatically sends back a response. Thus the communications are carried out without the PCs being actively involved.
Page 115 From the time this instruction is executed until the data transmission is com- plete, AR 0805 (or AR 0813 for the peripheral port) will remain OFF. It will turn ON again upon completion of the data transmission. The TXD(48) instruction does not provide for a response, so in order to receive confirmation that the computer has received the data, the computer’s program must be written so...
Page 116: Cpm1/Cpm1A Host Link Communications
08 to 11 Link area for one-to-one PC link via peripheral port 0: LR 00 to LR 15 (Any value is OK) 12 to 15 Communications mode 0: Host link; 2: One-to-one PC link (slave); 3: One-to-one PC link (master); 4: NT link...
Page 117 OK) Note 1. If an improper setting is used, a non-fatal error will occur, AR 1302 will be turned ON, and the default setting (0, 00, or 0000) will be used. 2. For information on the host link settings for another OMRON PC, refer to that PC’s Operation Manual.
Page 118: Srm1 Host Link Communications
0: Standard (1 start bit, 7-bit data, even parity, 2 stop bits, 9,600 bps) host 1: Settings in DM 6651 parame- ters (Other settings will cause a non-fatal error, the default setting (0) will be used, and AR 1302 will turn ON.) 04 to 07 Not used. 08 to 11 Not used.
Page 119 (Other settings will cause a non-fatal error, the default setting (0000) will be used, and AR 1302 will turn ON.) 08 to 11 Start code enable (RS-232C, effective when bits 12 to 15 of DM 6650 are set to 1.) 0: Disable 1: Set 12 to 15 End code enable (RS-232C, effective when bits 12 to 15 of DM 6650 are set to 1.)
Page 120 0: LR 00 to LR 15; Other: Not effective 12 to 15 Communications mode 0: Host link 0: Host link; 1: RS-232C (no protocol); 2: 1:1 data link slave; 3: 1:1 data link master; 4: NT Link DM 6646 00 to 07...
Page 121: Rs-232C Communications (Cqm1/Srm1 Only)
1-9-6 RS-232C Communications (CQM1/SRM1 Only) This section explains RS-232C communications. By using RS-232C commu- nications, the data can be printed out by a printer or read by a bar code reader. Handshaking is not supported for RS-232C communications. Communications Procedure Transmissions 1,2,3...
Page 122 256 bytes, N will be between 254 and 256 depending on the designations for start and end codes. If the number of bytes to be sent is set to 0000, only the start and end codes will be sent.
Page 123: Cqm1 One-To-One Link Communications
Section 1-9 Communications Functions The start code and end code are not included in AR 09 or AR 10 (number of bytes received). Application Example This example shows a program for using the RS-232C port in the RS-232C Mode to transmit 10 bytes of data (DM 0100 to DM 0104) to the computer, and to store the data received from the computer in the DM area beginning with DM 0200.
Page 124 IR 001 of each Unit will be reflected in IR 100 of the other Unit. Likewise, the status of the other Unit’s IR 001 will be reflected in IR 100 of each Unit. IR 001 is an input word and IR 100 is an output word...
Page 125: Cpm1/Cpm1A One-To-One Link Communications
CQM1, or a C200HS through an RS-232C Adapter and standard RS-232C cable. One of the PCs will serve as the master and the other as the slave. The one-to-one link can connect up to 256 bits (LR 0000 to LR 1515) in the two PCs.
Page 126: Cpm1/Cpm1A Nt Link Communications
Section 1-9 Communications Functions 4. If an out-of-range value is set, the following communications conditions will result. In that case, reset the value so that it is within the permissible range. Communications mode: Host Link Communications format: Standard settings (1 start bit, 7-bit data; even parity, 2 stop bits,...
Page 127: Srm1 One-To-One Link Communications
CQM1, or a C200HS through an RS-232C Adapter and standard RS-232C cable. One of the PCs will serve as the master and the other as the slave. The one-to-one link can connect up to 256 bits (LR 0000 to LR 1515) in the two PCs.
Page 128 Communications Functions Limitations of One-to-one Only the 16 LR words from LR 00 to LR 15 can be linked in the SRM1, so use Links with a SRM1 only those 16 words in the CQM1 or C200HS when making a one-to-one link with one of those PCs.
Page 129: Srm1 Nt Link Communications
08 to 11 Link area for one-to-one PC link via peripheral port 0: LR 00 to LR 15 12 to 15 Communications mode 0: Host link; 1: No protocol; 2: 1-to-1 PC link (slave); 3: 1-to-1 PC link (master); 4: NT link Note 1.
Page 130: Srm1 No Protocol Communications
(Other settings will cause a non-fatal error, the default setting (0000) will be used, and AR 1302 will turn ON.) 08 to 11 Start code enable (RS-232C, effective when bits 12 to 15 of DM 6650 are set to 1.) 0: Disable required...
Page 131 0: LR 00 to LR 15; Other: Not effective 12 to 15 Communications mode 1: No pro- 0: Host link; 1: RS-232C (no protocol); 2: 1:1 data link slave; 3: 1:1 data link master; tocol 4: NT Link DM 6646...
Page 132: Transmission Data Configuration
• End Code of CR, LF: Data (256 bytes max.) • Start Code 00-FF/End Code CR,LF: Data (256 bytes max.) Note 1. The start and end codes are set in DM 6648 to DM 6649 and DM 6653 to DM 6654 of the PC Setup.
Page 133: Transmission Flags
Communications Functions Section 1-9 2. When there are several start and end codes, the first part of each will be effective. 3. When the end code duplicates the transmission data and the transmission is stopped part way through, use CR or LF as the end code.
Page 134: Calculating With Signed Binary Data
Signed binary data is manipulated using 2’s complements and the MSB of the one- or two-word data is used as the sign bit. The range of data that can be expressed using one or two words is thus as follows: •...
Page 135 Calculating with Signed Binary Data Section 1-10 The following table shows equivalents between decimal and hexadecimal data. Decimal 16-bit Hex 32-bit Hex 2147483647 ––– 7FFFFFFF 2147483646 ––– 7FFFFFFE 32768 ––– 00008000 32767 7FFF 00007FFF 32766 7FFE 00007FFE 0002 00000002 0001...
Page 136: Arithmetic Flags
The results of executing signed binary instructions is reflected in the arith- metic flags. The flags and the conditions under which it will turn ON are given in the following table. The flags will be OFF when these conditions are not met.
Page 137: Application Example Using Signed Binary Data
Section 1-10 Calculating with Signed Binary Data 1-10-5 Application Example Using Signed Binary Data The following programming can be used to performed calculations such as the following in the CQM1: ((1234 + (–123)) x 1212 – 12345) (–1234) = –1081, Remainder of 232...
Page 138: Special Features
Alternate I/O Bits ........
Page 139: Expansion Instructions (Cqm1/Srm1 Only)
The mnemonics of expansion instructions are followed by “(––)” as the func- tion code to indicate that they must be assigned function codes by the user in the instructions table before they can be used in programming (unless they are used under their default settings).
Page 140: Cqm1 Expansion Instructions
The following 18 function codes can be used for expansion instructions: 17, 18, 19, 47, 48, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 87, 88, and 89 The expansion instructions that can be used are listed below, along with the default function codes that are assigned when the CQM1 is shipped.
Page 141: Advanced I/O Instructions (Cqm1 Only)
Prepare a 10-key keypad, and connect it so that the switches for numeric keys 0 through 9 are input to points 0 through 9 as shown in the following diagram. Either the input terminals on the CPU Unit or the inputs on a DC Input Unit with 16 or more input points can be used.
Page 142 DM 1000 and DM 1001. Key information is stored in DM 1002. IR 00015 is used as an “ENTER key,” and when IR 00015 turns ON, the data stored in DM 1000 and DM 1001 will be transferred to DM 0000 and DM 0001.
Page 143: Hexadecimal Key Input - Hky
Output Unit Input Unit The inputs can be connected to the input terminals on the CPU Unit or a DC Input Unit with 8 or more input points and the outputs can be connected from a Transistor Output Unit with 8 points or more.
Page 144 4. If more than eight digits are input, digits will be deleted beginning with the leftmost digit. 5. Input and output bits not used here can be used as ordinary input and out- put bits. With this instruction, one key input is read in 3 to 12 cycles. More than one cycle is required because the ON keys can only be determined as the outputs are turned ON to test them.
Page 145: Digital Switch Input - Dsw(87)
D0 through D3 from the digital switch to input points 0 through 3. In either case, output point 5 will be turned ON when one round of data is read, but there is no need to connect output point 5 unless required for the application.
Page 146 Number of digits to read 00: 4 digits 01: 8 digits Default: 4 digits Do not make any changes to bits 0 to 7. They are not related to DSW(87). Using the Instruction DSW(87) IW: Input word OW: Output word...
Page 147 HR51 DM0000 Note Output point 5 (here, IR 10005) turns on when one round of data is read and can be used to time switching the data storage area and gate signal (CS sig- nal) when DSW(87) is used to input data to different areas of memory.
Page 148: 7-Segment Display Output - 7Seg
O: Output word C: Control data If the first word holding the data to be displayed is specified at S, and the out- put word is specified at O, and the SV taken from the table below is specified at C, then operation will proceed as shown below when the program is exe- cuted.
Page 149 This example shows a program for displaying the CQM1’s 8-digit BCD num- bers at the 7-segment LED display. Assume that the 7-segment display is connected to output word IR 100. Also assume that the Output Unit is using negative logic, and that the 7-segment display logic is also negative for data signals and latch signals.
Page 150: Alternate I/O Bits
Section 2-2 Advanced I/O Instructions (CQM1 Only) The 8-digit BCD data in DM 0120 (rightmost 4 digits) and DM 0121 (leftmost 4 digits) are always displayed by means of 7SEG(88). When the contents of DM 0120 and DM 0121 change, the display will also change.
Page 151: Macro Function
(step 3 above). Note 1. In CQM1 PCs, IR 096 to IR 099 and IR 196 to IR 199 can be used as work bits when MCRO(99) is not used. 2. In CPM1/CPM1A/SRM1 PCs, SR 232 through SR 239 can be used as work bits when MCRO(99) is not used.
Page 152: Differential Monitor
The CPM1/CPM1A/SRM1 program can be simplified like the one shown Application Example above, but words SR 232 through SR 235 would be used instead of IR 096 through IR 099 and words SR 236 through SR 239 would be used instead of IR 196 through IR 199.
Page 153: Analog Settings (Cqm1-Cpu42-Ev1/Cpm1/Cpm1A Only)
In the CQM1-CPU42-EV1/CPM1/CPM1A PCs, the analog settings function automatically transfers the settings on the CPU Unit’s adjustment switches to IR 220 through IR 223. This function is very useful when there are set values that need to be precisely adjusted during operation. These set values can be changed just by turning the adjustment switches on the CPU Unit.
Page 154: Quick-Response Inputs (Cpm1/Cpm1A Only)
Quick-response Operation Quick-response inputs have an internal buffer, so input signals shorter than one cycle can be detected. Signals with a pulse width as short as 0.2 ms can be detected, regardless of their timing during the PC cycle. Overseeing...
Page 155 Section 2-6 Quick-response Inputs (CPM1/CPM1A Only) Setting Quick-response The input bits in the above table can be set as quick-response inputs in Inputs DM 6628, as shown in the following table. Word Settings DM 6628 0: Normal input 1: Interrupt input...
Page 156: Memory Areas
Memory Cassette operations used to transfer data between the CQM1 CPU Unit and a Memory Cassette. CQM1 Memory Area Functions ........
Page 157: Cqm1 Memory Area Functions
IR 000 to IR 015 IR 00000 to IR 01515 CQM1-CPU11/21-E: Up to 8 words IR area (128 bits) can be used for I/O bits. Up to 7 bits Units can be connected. Output area IR 100 to IR 115...
Page 158 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. At least 2,720 bits can be used as work bits. The total number of bits that can be used depends on the configuration of the PC system.
Page 159 CQM1-CPU44-EV1, they are used by the system. They can be used as work bits in other CPU Units. IR 200 to IR 215 and IR 240 to IR 243 will be used in future functions, but they can be used as work bits for the time being.
Page 160 Input Unit OUT: Output Unit The number of allocated input words is stored in BCD in AR 2200 to AR 2207; the number of allocated output words in BCD in AR 2208 to AR 2215. The CQM1 PCs do not use an I/O table.
Page 161 TC number are used to create timers and counters, as well as to access Com- pletion Flags and present values (PVs). If a TC number is designated for word data, it will access the present value (PV); if it is used for bit data, it access the Completion Flag for the timer/counter.
Page 162 1. The CQM1-CPU11-E and CQM1-CPU21-E do not support DM 1024 through DM 6143. 2. Turning ON pin 1 of the DIP switch on the CPU Unit will prevent writing even by means of peripheral devices. Fixed DM contents, the PC Setup, the user program, and the instructions table can all be saved to and loaded from a Memory Cassette as a single unit.
Page 163: Cpm1/Cpm1A Memory Area Functions
(56 words) trol PC operation. Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. The contents of the HR area, LR area, Counter area, and read/write DM area are backed up by a capacitor. The backup time varies with the ambi- ent temperature, but at 25 C, the capacitor will back up memory for 20 days.
Page 164 The functions of the IR area are explained below. I/O Bits IR area bits from IR 00000 to IR 01915 are allocated to terminals on the CPU Unit and I/O Units. They reflect the ON/OFF status of input and output signals.
Page 165 TC numbers are used to create timers and counters, as well as to access Completion Flags and present values (PVs). If a TC number is designated for word data, it will access the present value (PV); if it is used for bit data, it will access the Completion Flag for the timer/counter.
Page 166: Srm1 Memory Area Functions
SRM1 Memory Area Functions 3-2-9 DM Area DM area data is accessed in word units only. The contents of the DM area are retained even after the CPM1/CPM1A power supply has been turned off or when operation begins or stops.
Page 167 (56 words) trol PC operation. Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. The contents of the HR area, LR area, Counter area, and read/write DM area are backed up by a capacitor. At 25 C, the capacitor will back up memory for 20 days.
Page 168 TC numbers are used to create timers and counters, as well as to access Completion Flags and present values (PVs). If a TC number is designated for word data, it will access the present value (PV); if it is used for bit data, it will access the Completion Flag for the timer/counter.
Page 169: Srm1 Flash Memory
In order to write the contents of the UM area, the DM read-only area (DM 6144 to DM 6599, and the PC Setup area (DM 6600 to DM 6655) to the flash memory, either one of the following operations must be performed.
Page 170: Using Memory Cassettes (Cqm1 Only)
3-5-2 Memory Cassette Capacity and UM Area Size A non-fatal error will occur if an attempt is made to transfer a program that is too large. There are two cases in which this can occur. 1,2,3...
Page 171: Nop(00)
8-KW or larger Memory Cassettes only. In CQM1-CPU11/21-E CPU Units, the content of AR 1508 to AR 1515 is nor- mally 04, and the content of AR 1500 to AR 1507 is normally 04 when a 4-KW Memory Cassette is installed.
Page 172 CQM1 power supply off and remove the Memory Cassette before changing the switch. 2. Check to see that the CQM1 is in PROGRAM mode. If it is in either RUN or MONITOR mode, use the LSS/SSS to change the mode.
Page 173: Operation Without A Battery
Memory Cassette. Use the following procedure. 1,2,3... 1. Check to see that the CQM1 is in PROGRAM mode. If it is in either RUN or MONITOR mode, use the peripheral device to change to the PRO- GRAM mode.
Page 174 (Turns ON for 1 cycle at the start of operation.) Note If the setting shown below is made in the PC Setup (DM 6655 bits 12 to 15), battery errors (a non-fatal error) will not be detected even if the internal bat- tery expires.
Page 175 Section 3-6 Operation without a Battery...
Page 176: Ladder-Diagram Programming
Ladder Instructions ........
Page 177: Basic Procedure
I/O bit allocated to each I/O de- vice. 2. If you are using LR bits to link two PCs, prepare sheet showing the used of these bits. 3. Determine what words are available for work bits and prepare a table in which you can allocate these as you use them.
Page 178: Basic Ladder Diagrams
A ladder diagram consists of one line running down the left side with lines branching off to the right. The line on the left is called the bus bar; the branch- ing lines, instruction lines or rungs. Along the instruction lines are placed con- ditions that lead to other instructions on the right side.
Page 179: Mnemonic Code
The operands designated for any of the ladder instructions can be any bit in the IR, SR, HR, AR, LR, or TC areas. This means that the conditions in a lad- der diagram can be determined by I/O bits, flags, work bits, timers/counters, etc.
Page 180: Ladder Instructions
If the instruction requires no definer or bit operand, the operand column is left blank for first line. It is a good idea to cross through any blank data col- umn spaces (for all instruction words that do not require data) so that the data column can be quickly scanned to see if any addresses have been left out.
Page 181 When this is the only condition on the instruction line, the execution condition for the instruction at the right is ON when the condition is ON. For the LOAD instruction (i.e., a normally open condition), the execution condition would be ON when IR 00000 was ON;...
Page 182: Or Not
LOAD NOT instruction; the rest of the conditions correspond to OR or OR NOT instructions. The following example shows three conditions which corre- spond in order from the top to a LOAD NOT, an OR NOT, and an OR instruc- tion. Again, each of these instructions requires one line of mnemonic code.
Page 183: Output And Output Not
OUT NOT 10001 In the above examples, IR 10000 will be ON as long as IR 00000 is ON and IR 10001 will be OFF as long as IR 00001 is ON. Here, IR 00000 and IR 00001 would be input bits and IR 10000 and IR 10001 output bits assigned to the Units controlled by the PC, i.e., the signals coming in through the input points...
Page 184: Logic Block Instructions
OR. What we need is a way to do the OR (NOT)’s independently and then combine the results. To do this, we can use the LOAD or LOAD NOT instruction in the middle of an instruction line. When LOAD or LOAD NOT is executed in this way, the current execution condition is saved in special buffers and the logic process is begun over.
Page 185 An ON execution condition would be pro- duced for the instruction at the right either when IR 00000 is ON and IR 00001 is OFF or when IR 00002 and IR 00003 are both ON. The operation of and...
Page 186 10000 Again, with the method on the right, a maximum of eight blocks can be com- bined. There is no limit to the number of blocks that can be combined with the first method. The following diagram requires OR LOAD instructions to be converted to mnemonic code because three pairs of conditions in series lie in parallel to each other.
Page 187 00007 10001 Although the following diagram is similar to the one above, block b in the dia- gram below cannot be coded without separating it into two blocks combined with OR LOAD. In this example, the three blocks have been coded first and...
Page 188 combined.
Page 189 The following diagram must be broken down into two blocks and each of these then broken into two blocks before it can be coded. As shown below, blocks a and b require an AND LOAD. Before AND LOAD can be used, however, OR LOAD must be used to combine the top and bottom blocks on both sides, i.e.,...
Page 190 Section 4-3 Basic Ladder Diagrams The following diagram requires an OR LOAD followed by an AND LOAD to code the top of the three blocks, and then two more OR LOADs to complete the mnemonic code. 00000 00001 Address Instruction...
Page 191 00002 00007 OR LD 00008 00000 00009 0000 The next and final example may at first appear very complicated but can be coded using only two logic block instructions. The diagram appears as follows: Block a 00000 00001 00002 00003...
Page 192 Section 4-3 The first logic block instruction is used to combine the execution conditions resulting from blocks a and b, and the second one is to combine the execution condition of block c with the execution condition resulting from the normally closed condition assigned IR 00003.
Page 193: Coding Multiple Right-Hand Instructions
This is because instruction lines are exe- cuted across to a right-hand instruction before returning to the branching point to execute instructions one a branch line. If a condition exists on any of the instruction lines after the branching point, the execution condition could change during this time making proper execution impossible.
Page 194 IL(03)). TR Bits The TR area provides eight bits, TR 0 through TR 7, that can be used to tem- porarily preserve execution conditions. If a TR bit is placed at a branching point, the current execution condition will be stored at the designated TR bit.
Page 195 IR 00004 and the second time for an AND with the inverse of the status of IR 00005. TR bits can be used as many times as required as long as the same TR bit is not used more than once in the same instruction block. Here, a new instruc- tion block is begun each time execution returns to the bus bar.
Page 196 00006 ILC(03) If IR 00000 is ON in the revised version of diagram B, above, the status of IR 00001 and that of IR 00002 would determine the execution conditions for instructions 1 and 2, respectively. Because IR 00000 is ON, this would pro- duce the same results as ANDing the status of each of these bits.
Page 197: Jumps
A jump can be defined using jump numbers 01 through 99 only once, i.e., each of these numbers can be used once in a JUMP instruction and once in a JUMP END instruction. When a JUMP instruction assigned one of these num-...
Page 198: Controlling Bit Status
Although these instructions are used to turn ON and OFF output bits in the IR area (i.e., to send or stop output signals to external devices), they are also used to control the status of other bits in the IR area or in other data areas.
Page 199: Differentiate Up And Differentiate Down
DIFD(14) 01001 Here, IR 01000 will be turned ON for one cycle after IR 00000 goes ON. The next time DIFU(13) 01000 is executed, IR 01000 will be turned OFF, regard- less of the status of IR 00000. With the DIFFERENTIATE DOWN instruction,...
Page 200: Work Bits (Internal Relays)
In the following example, HR 0000 will be turned ON when IR 00002 is ON and IR 00003 is OFF. HR 0000 will then remain ON until either IR 00004 or IR 00005 turns ON. With KEEP, as with all instructions requiring more than one instruction line, the instruction lines are coded first before the instruction that they control.
Page 201 In this exam- ple, IR 10000 must be left ON continuously as long as IR 001001 is ON and both IR 00002 and IR 00003 are OFF, or as long as IR 00004 is ON and IR...
Page 202: Programming Precautions
ON, IR 22500 will be turned ON for one cycle and then be turned OFF the next cycle by DIFU(13). Assuming the other conditions controlling IR 10000 are not keeping it ON, the work bit IR 22500 will turn IR 10000 ON for one cycle only.
Page 203 Again, diagram A , below, must be drawn as diagram B. If an instruction must be continuously executed (e.g., if an output must always be kept ON while the program is being executed), the Always ON Flag (SR 25313) in the SR area can be used.
Page 204: Program Execution
Program execution is only one of the tasks carried out by the CPU Unit as part of the cycle time. Refer to SECTION 7 PC Operations and Processing Time...
Page 206: Instruction Set
Ladder Diagram Instructions ........
Page 207 5-19-10 SCALING – SCL(66) ........
Page 208 5-27 Communications Instructions ........
Page 209: Notation
In this section, each instruction description includes its ladder diagram sym- bol, the data areas that can be used by its operands, and the values that can be used as definers. Details for the data areas are also specified by the oper- and names and the type of data required for each operand (i.e., word or bit...
Page 210 When an indirect DM address is specified, the designated DM word will con- tain the address of the DM word that contains the data that will be used as the operand of the instruction. If, for example, *DM 0001 was designated as the...
Page 211: Differentiated Instructions
DIFU(13) operates the same as a differentiated instruction, but is used to turn ON a bit for one cycle. DIFD(14) also turns ON a bit for one cycle, but does it when the execution condition has changed from ON to OFF. Refer to 5-8-4...
Page 212: Coding Right-Hand Instructions
If an IR or SR address is used in the data column, the left side of the column is left blank. If any other data area is used, the data area abbreviation is placed on the left side and the address is placed on the right side.
Page 213: Tim 000
Section 5-5 Coding Right-hand Instructions The following diagram and corresponding mnemonic code illustrates the points described above. Address Instruction Data 00000 00001 DIFU(13) 21600 00000 00000 00002 00001 00001 00002 00002 00003 DIFU(13) 21600 00100 00200 21600 BCNT(67) 00004 00100...
Page 214 KEEP(11)), all of the lines for the instruction are entered before the right-hand instruction. Each of the lines for the instruction is coded, starting with LD or LD NOT, to form `logic blocks’ that are combined by the right-hand instruction.
Page 215: Instruction Tables
This section provides tables of the instructions available in the CQM1. The first few tables can be used to find instructions by function code. The last table can be used to find instructions by mnemonic. In both tables, the @ symbol indicates instructions with differentiated forms.
Page 216: Cpm1/Cpm1A Function Codes
The following table lists the CPM1/CPM1A instructions that have fixed func- tion codes. Each instruction is listed by mnemonic and by instruction name. Use the numbers in the leftmost column as the left digit and the number in the column heading as the right digit of the function code.
Page 217: Srm1 Function Codes
The following table lists the SRM1 instructions that have fixed function codes. Each instruction is listed by mnemonic and by instruction name. Use the num- bers in the leftmost column as the left digit and the number in the column heading as the right digit of the function code.
Page 218: Alphabetic List By Mnemonic
Section 5-6 Instruction Tables 5-6-4 Alphabetic List by Mnemonic Dashes (“–”) in the Code column indicate expansion instructions, which do not have fixed function codes. “None” indicates instructions for which function codes are not used. Mnemonic Code Words Name CPU Units...
Page 219: Max (@)
Section 5-6 Instruction Tables Mnemonic Code Words Name CPU Units Page DVB (@) BINARY DIVIDE FAL (@) FAILURE ALARM AND RESET FALS SEVERE FAILURE ALARM FCS (@) –– FCS CALCULATE CQM1/SRM1 only –– FAILURE POINT DETECT CQM1 only HEX (@) ––...
Page 220: Pwm (@)
Words Name CPU Units Page PULS (@) SET PULSES CQM1 and CPM1A-@@CDT/CDT1 only PWM (@) –– PULSE WITH VARIABLE DUTY RATIO CQM1-CPU43-E/-EV1 only SUBROUTINE RETURN ROL (@) ROTATE LEFT ROOT (@) SQUARE ROOT CQM1 only ROR (@) ROTATE RIGHT RSET...
Page 221: Ladder Diagram Instructions
IR, SR, AR, HR, TC, LR Limitations There is no limit to the number of any of these instructions, or restrictions in the order in which they must be used, as long as the memory capacity of the PC is not exceeded. Description These six basic instructions correspond to the conditions on a ladder diagram.
Page 222: Bit Control Instructions
AND LD and OR LD logically combine two execution conditions, the current one and the last unused one. In order to draw ladder diagrams, it is not necessary to use AND LD and OR LD instructions, nor are they necessary when inputting ladder diagrams directly, as is possible from the SSS.
Page 223: Set And Reset - Set And Rset
The length of time that a bit is ON or OFF can be controlled by combining the OUT or OUT NOT with TIM. Refer to Examples under 5-15-1 TIMER – TIM for details.
Page 224: Keep - Keep(11)
Section 5-8 Bit Control Instructions In the second example (Diagram B), IR 10000 will be turned ON when IR 00001 goes ON and will remain ON (even if IR 00001 goes OFF) until IR 00002 goes ON. 00000 Address Instruction...
Page 225: Differentiate Up And Down - Difu(13) And Difd(14
ON and the current execution condition is either ON or OFF, DIFU(13) will either turn the designated bit OFF or leave it OFF (i.e., if the designated bit is already OFF). The designated bit will thus never be ON for longer than one cycle, assuming it is executed each cycle (see Precau- tions, below).
Page 226: No Operation - Nop(00)
5-26-8 INTERRUPT CONTROL – INT(89). Example In this example, IR 10014 will be turned ON for one cycle when IR 00000 goes from OFF to ON. IR 10015 will be turned ON for one cycle when IR 00000 goes from ON to OFF.
Page 227 The interlock is in effect while 00000 is OFF. Notice that 01000 is not turned ON at the point labeled A even though 00001 has turned OFF and then back ON.
Page 228: Jump And Jump End - Jmp(04) And Jme(05)
When the execution condition for the first IL(02) is OFF, TIM 127 will be reset to 1.5 s, CNT 001 will not be changed, and 00502 will be turned OFF. When the execution condition for the first IL(02) is ON and the execution condition for the second IL(02) is OFF, TIM 127 will be executed according to the status of 00001, CNT 001 will not be changed, and 00502 will be turned OFF.
Page 229: Jmp(04) And Jme(05)
In a jump, this means the next time the jump from JMP(04) to JME(05) is not made, i.e., if a bit is turned ON by DIFU(13) or DIFD(14) and then a jump is made in the next cycle so that DIFU(13) or DIFD(14) are skipped, the designated bit will remain ON until the next time the execution condition for the JMP(04) controlling the jump is ON.
Page 230: User Error Instructions: Failure Alarm And Reset - Fal(06) And Severe Failure Alarm - Fals
ON execution condition, either of these instructions will output a FAL number to bits 00 to 07 of SR 253. The FAL number that is output can be between 01 and 99 and is input as the definer for FAL(06) or FALS(07).
Page 231: Step Instructions: Step Define And Step Start-Step(08)/Snxt(09)
STEP(08) is executed without a control bit. STEP(08) without a control bit must be preceded by SNXT(09) with a dummy control bit. The dummy control bit may be any unused IR or HR bit. It cannot be a control bit used in a STEP(08).
Page 232: Snxt(09)
OFF the control bit for the step (see example 3 below). When the step is completed, all of the IR and HR bits in the step are turned OFF and all timers in the step are reset to their SVs. Counters, shift registers, and bits used in KEEP(11) maintain status.
Page 233: Timer And Counter Instructions
TC number as a definer in a timer or counter instruction. Once defined as a timer, a TC number can be prefixed with TIM for use as an operand in certain instructions. The TIM prefix is used regardless of the timer instruction that was used to define the timer.
Page 234: Timer - Tim
The same is true of all other TC numbers prefixed with TIM or CNT. An SV can be input as a constant or as a word address in a data area. If an IR area word assigned to an Input Unit is designated as the word address, the Input Unit can be wired so that the SV can be set externally through thumb- wheel switches or similar devices.
Page 235: Counter - Cnt
PV reaches zero and will remain ON until the counter is reset. CNT is reset with a reset input, R. When R goes from OFF to ON, the PV is reset to SV. The PV will not be decremented while R is ON. Counting down from SV will begin again when R goes OFF.
Page 236 SR area clock pulse bits. CNT 001 counts the number of times the 1-second clock pulse bit (SR 25502) goes from OFF to ON. Here again, IR 00000 is used to control the times when CNT is operating. Because in this example the SV for CNT 001 is 700, the Completion Flag for CNT 002 turns ON when 1 second x 700 times, or 11 minutes and 40 seconds have expired.
Page 237: Reversible Counter - Cntr(12)
When decremented from 0000, the present value is set to SV and the Com- pletion Flag is turned ON until the PV is decremented again. When incre- mented past the SV, the PV is set to 0000 and the Completion Flag is turned ON until the PV is incremented again.
Page 238: High-Speed Timer - Timh(15)
Timers in jumped program sections will not be reset when the execution con- dition for JMP(04) is OFF, but the timer will stop timing if jump number 00 is used. The timers will continue timing if jump numbers 01 through 99 (01 through 49 in CPM1/CPM1A/SRM1 PCs) are used.
Page 239: Interval Timer - Stim(69)
If C1 is 000 to 005, a constant greater than 0255 cannot be used for C3. If C1 is 006 to 008, constants and DM 6143 to DM 6655 cannot be used for C2 or C3. If C1 is 010 to 012, both C2 and C3 must be set to 000. Limitations C1 must be 000, 003, 006.
Page 240 CPM1A/SRM1 CQM1 only Note 1. In CQM1 PCs, interval timer 0 cannot be used when a pulse output is being output by the SPED(64) instruction. 2. In CQM1 PCs, interval timer 2 cannot be used when high-speed counter 0 operation has been enabled in DM 6642 of the PC Setup.
Page 241: Register Comparison Table - Ctbl(63)
This instruction is not available for SRM1 PCs. Limitations The first and last comparison table words must be in the same data area. (The length of the comparison table varies according to the settings.) In the CQM1-CPU43-EV1, CTBL(63) cannot be used if the PC Setup (DM 6611) is set to pulse output mode.
Page 242 Subroutine number (See note.) The following diagram shows the structure of a target value comparison table for use with high-speed counters 1 or 2 in ring mode. Input the target values in ascending or descending order. The ring value specifies the number of points in the ring and the maximum count value (ring value = max.
Page 243 When all target values in the comparison table have been matched and interrupts for them generated, the target value is reset to the first target value in the table and the operation is repeated.
Page 244 Timer and Counter Instructions There are flags in the AR area which indicate when a high-speed counter’s PV falls within one or more of the 8 ranges. The flags turn ON when a PV is within the corresponding range. Counter...
Page 245 CPU11/21-E, 0000 to 0049 for the CPM1/CPM1A) to activate the subrou- tine when incrementing. 3. Allow a time interval of at least 2 ms between the lower and upper limits (upper limit – lower limit > 0.002 input pulse frequency) in range compar- isons with high-speed counters 1 and 2.
Page 246: Mode Control - Ini(61)
Subroutines are executed only once when the execution conditions are first met. AR status is refreshed only once per cycle. If conditions are met for more than one item in the table at the same time, the first item in the table takes pri- ority.
Page 247 Interrupts (CPM1/CPM1A PCs) for details on table comparison. PV Change If C is 002, INI(61) changes the high-speed counter’s PV to the 8-digit value in P1 and P1+1. With high-speed counter 0, the PV can be F003 2767 to 0003 2767 in Up/ Down Mode, or 0000 0000 to 0006 5535 in Incremental Mode.
Page 248: High-Speed Counter Pv Read - Prv(62)
With high-speed counter 0, the PV can be F003 2767 to 0003 2767 in Up/ Down Mode, or 0000 0000 to 0006 5535 in Incremental Mode. The hexadeci- mal value F in the most significant digit of PV indicates that the PV is negative. Leftmost 4 digits...
Page 249 D (01 through 15) are not used and will always be 0. Note These flags are in AR 05 and AR 06, but those words are normally refreshed only once each cycle, so the data obtained with PRV(62) will be more up-to- date.
Page 250: Shift Instructions
IR, SR, AR, HR, LR Limitations E must be greater than or equal to St, and St and E must be in the same data area. If a bit address in one of the words used in a shift register is also used in an instruction that controls individual bit status (e.g., OUT, KEEP(11)), an error...
Page 251: Word Shift - Wsft(16)
E: End word IR, SR, AR, DM, HR, LR Limitations St and E must be in the same data area, and E must be greater than or equal to St. DM 6144 to DM 6655 cannot be used for St or E.
Page 252: Arithmetic Shift Right - Asr(26)
When the execution condition is OFF, ASL(25) is not executed. When the exe- cution condition is ON, ASL(25) shifts a 0 into bit 00 of Wd, shifts the bits of Wd one bit to the left, and shifts the status of bit 15 into CY.
Page 253: Rotate Right - Ror(28)
ON, ROL(27) shifts all Wd bits one bit to the left, shifting CY into bit 00 of Wd and shifting bit 15 of Wd into CY. 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 Precautions...
Page 254: One Digit Shift Left - Sld(74)
St: Starting word IR, SR, AR, DM, HR, LR Limitations St and E must be in the same data area, and E must be less than or equal to DM 6144 to DM 6655 cannot be used for St or E.
Page 255: Reversible Shift Register - Sftr(84)
When the execution condition is OFF, SRD(75) is not executed. When the execution condition is ON, SRD(75) shifts data between St and E (inclusive) by one digit (four bits) to the right. 0 is written into the leftmost digit of St and the rightmost digit of E is lost.
Page 256: Asynchronous Shift Register - Asft(17)
Section 5-16 Shift Instructions the reset bit is OFF and as long as bit 14 is ON. If SFTR(84) is executed with an OFF execution condition or if SFTR(84) is executed with bit 14 OFF, the shift register will remain unchanged. If SFTR(84) is executed with an ON exe- cution condition and the reset bit (bit 15) is OFF, the entire shift register and CY will be set to zero.
Page 257 E. Control Word Bits 00 through 12 of C are not used. Bit 13 is the shift direction: turn bit 13 ON to shift down (toward lower addressed words) and OFF to shift up (toward higher addressed words). Bit 14 is the Shift Enable Bit: turn bit 14 ON to enable shift register operation according to bit 13 and OFF to disable the reg- ister.
Page 258: Data Movement Instructions
Section 5-17 Data Movement Instructions Note The zeroes are shifted “upward” if C=4000, and the entire shift register is set to zero if C=8000. 5-17 Data Movement Instructions 5-17-1 MOVE – MOV(21) Ladder Symbols Operand Data Areas S: Source word...
Page 259: Move Not - Mvn(22)
ON, MVN(22) transfers the inverted content of S (spec- ified word or four-digit hexadecimal constant) to D, i.e., for each ON bit in S, the corresponding bit in D is turned OFF, and for each OFF bit in S, the corre- sponding bit in D is turned ON.
Page 260: Block Transfer - Xfer(70)
IR, SR, AR, DM, HR, TC, LR Limitations St must be less than or equal to E, and St and E must be in the same data area. DM 6144 to DM 6655 cannot be used for St or E.
Page 261: Data Exchange - Xchg(73)
BCD, or the DM area boundary has been exceeded.) Example The following example shows how to use BSET(71) to copy a constant (#0000) to a block of the DM area (DM 0000 to DM 0500) when IR 00000 is 00000 Address Instruction...
Page 262: Single Word Distribute - Dist(80)
Example The following example shows how to use DIST(80) to copy #00FF to HR 10 + Of. The content of LR 10 is #3005, so #00FF is copied to HR 15 (HR 10 + 5) when IR 00000 is ON.
Page 263: Data Collect - Coll(81)
Data Movement Instructions Section 5-17 content of DBs. In other words, 1 and the content of DBs are added to DBs to determine the destination word. The content of DBs is then incremented by 1. Note 1. DIST(80) will be executed every cycle unless the differentiated form (@DIST(80)) is used or DIST(80) is used with DIFU(13) or DIFD(14).
Page 264 When bits 12 to 15 of C=9, COLL(81) can be used for an FIFO stack opera- tion. The other 3 digits of C specify the number of words in the stack (000 to 999). The content of SBs is the stack pointer.
Page 265 When bits 12 to 15 of C=8, COLL(81) can be used for an LIFO stack opera- tion. The other 3 digits of C specify the number of words in the stack (000 to 999). The content of SBs is the stack pointer.
Page 266: Move Bit - Movb(82)
ON, MOVB(82) copies the specified bit of S to the spec- ified bit in D. The bits in S and D are specified by Bi. The rightmost two digits of Bi designate the source bit; the leftmost two bits designate the destination bit.
Page 267: Move Digit - Movd(83)
ON, MOVD(83) copies the content of the specified digit(s) in S to the specified digit(s) in D. Up to four digits can be transferred at one time. The first digit to be copied, the number of digits to be copied, and the first digit to receive the copy are designated in Di as shown below.
Page 268: Transfer Bits - Xfrb
In the following example, XFRB(––) is used to transfer 5 bits from IR 020 and IR 021 to LR 00 and LR 01. The starting bit in IR 020 is D (13), and the start- ing bit in LR 00 is E (14), so IR 02013 to IR 02101 are copied to LR 0014 to LR 0102.
Page 269: Comparison Instructions
The following example shows how to save the comparison result immediately. Saving CMP(20) Results If the content of HR 09 is greater than that of 010, 10200 is turned ON; if the two contents are equal, 10201 is turned ON; if content of HR 09 is less than that of 010, 10202 is turned ON.
Page 270 R is set, e.g., if the CD equals the content of TB, bit 00 is turned ON, if it equals that of TB+1, bit 01 is turned ON, etc. The rest of the bits in R will be turned OFF.
Page 271: Block Compare - Bcmp(68)
If CD is found to be within any of these ranges (inclusive of the upper and lower limits), the corresponding bit in R is set. The comparisons...
Page 272 Section 5-18 Comparison Instructions that are made and the corresponding bit in R that is set for each true compar- ison are shown below. The rest of the bits in R will be turned OFF. CB+1 Bit 00 CB+2 CB+3...
Page 273: Double Compare - Cmpl(60)
The following example shows how to save the comparison result immediately. Saving CMPL(60) Results If the content of HR 10, HR 09 is greater than that of 011, 010, then 10000 is turned ON; if the two contents are equal, 10001 is turned ON; if content of HR 10, HR 09 is less than that of 011, 010, then 10002 is turned ON.
Page 274: Multi-Word Compare - Mcmp(19)
TB1+1 to TB2+1, TB1+2 to TB2+2, ..., and TB1+15 to TB2+15. If the first pair is equal, the first bit in R is turned OFF, etc., i.e., if the content of TB1 equals the content of TB2, bit 00 is turned OFF, if the content of TB1+1 equals the content of TB2+1, bit 01 is turned OFF, etc.
Page 275: Signed Binary Compare - Cps
When the execution condition is OFF, CPS(––) is not executed. When the exe- cution condition is ON, CPS(––) compares the 16-bit (4-digit) signed binary contents in Cp1 and Cp2 and outputs the result to the GR, EQ, and LE flags in the SR area.
Page 276: Double Signed Binary Compare - Cpsl(--)
Cp1 = Cp2 Cp1 > Cp2 Example In the following example, the content of 102 is greater than that of DM 0020, so 10000 is turned ON and the other bits, 10001 and 10002, are turned OFF. Address Instruction Operands...
Page 277: Area Range Compare - Zcp(--)
Cp1+1, Cp1 = Cp2+1, Cp2 Cp1+1, Cp1 > Cp2+1, Cp2 Example In the following example, the content of 103, 102 is less than that of DM 0021, DM 0020, so 10002 is turned ON and the other bits, 10000 and 10001, are turned OFF.
Page 278 Section 5-18 Comparison Instructions limit LL and upper limit UL and outputs the result to the GR, EQ, and LE flags in the SR area. The resulting flag status is shown in the following table. Comparison result Flag status GR (SR 25505)
Page 279: Conversion Instructions
ON, ZCPL(––) compares the 8-digit value in CD, CD+1 to the range defined by lower limit LL+1,LL and upper limit UL+1,UL and out- puts the result to the GR, EQ, and LE flags in the SR area. The resulting flag status is shown in the following table.
Page 280: Binary-To-Bcd - Bcd(24)
DM 6144 to DM 6655 cannot be used for R. Description BCD(24) converts the binary (hexadecimal) content of S into the numerically equivalent BCD bits, and outputs the BCD bits to R. Only the content of R is changed; the content of S is left unchanged. Binary...
Page 281: Double Bcd-To-Double Binary - Binl(58)
When the execution condition is OFF, BINL(58) is not executed. When the execution condition is ON, BINL(58) converts an eight-digit number in S and S+1 into 32-bit binary data, and outputs the converted data to R and R+1. S + 1...
Page 282: 4-To-16 Decoder - Mlpx(76)
ON, MLPX(76) converts up to four, four-bit hexadecimal digits from S into decimal values from 0 to 15, each of which is used to indi- cate a bit position. The bit whose number corresponds to each converted value is then turned ON in a result word.
Page 283 S. The final word required to store the converted result (R plus the number of digits to be converted) must be in the same data area as R, e.g., if two digits are converted, the last word address in a data area cannot be designated; if three digits are converted, the last two words in a data area cannot be desig- nated.
Page 284: 16-To-4 Encoder - Dmpx(77)
Section 5-19 Conversion Instructions Example The following program converts digits 1 to 3 of data from DM 0020 to bit posi- tions and turns ON the corresponding bits in three consecutive words starting with HR 10. Digit 0 is not converted.
Page 285 Up to four digits from four consecutive source words starting with S may be encoded and the digits written to R in order from the designated first digit. If more digits are designated than remain in R (counting from the designated first digit), the remaining digits will be placed at digits starting back at the beginning of R.
Page 286: 7-Segment Decoder - Sdec(78)
When 00000 is ON, the following diagram encodes IR words 010 and 011 to the first two digits of HR 10 and then encodes LR 10 and 11 to the last two digits of HR 10. Although the status of each source word bit is not shown, it is assumed that the bit with status 1 (ON) shown is the highest bit that is ON in the word.
Page 287 Any or all of the digits in S may be converted in sequence from the designated first digit. The first digit, the number of digits to be converted, and the half of D to receive the first 7-segment display code (rightmost or leftmost 8 bits) are designated in Di.
Page 288 Conversion Instructions Example The following example shows the data to produce an 8. The lower case letters show which bits correspond to which segments of the 7-segment display. The table underneath shows the original data and converted code for all hexadec- imal digits.
Page 289: Ascii Convert - Asc(86)
8-bit ASCII code and places it into the destination word(s) begin- ning with D. Any or all of the digits in S may be converted in order from the designated first digit. The first digit, the number of digits to be converted, and the half of D to receive the first ASCII code (rightmost or leftmost 8 bits) are designated in Di.
Page 290: Ascii-To-Hexadecimal - Hex
Parity The leftmost bit of each ASCII character (2 digits) can be automatically adjusted for either even or odd parity. If no parity is designated, the leftmost bit will always be zero. When even parity is designated, the leftmost bit will be adjusted so that the total number of ON bits is even, e.g., when adjusted for even parity, ASCII “31”...
Page 291 All source words must be in the same data area. Bytes in the source words must contain the ASCII code equivalent of hexa- decimal values, i.e., 30 to 39 (0 to 9) or 41 to 46 (A to F). DM 6144 to DM 6655 cannot be used for D.
Page 292 The leftmost bit of each ASCII character (2 digits) is automatically adjusted for either even or odd parity. With no parity, the leftmost bit should always be zero. With odd or even parity, the leftmost bit of each ASCII character should be adjusted so that there is an...
Page 293: Scaling - Scl(66)
Conversion Instructions Section 5-19 If the parity of the ASCII code in S does not agree with the parity specified in Di, the ER Flag (SR 25503) will be turned ON and the instruction will not be executed. Flags Incorrect digit designator, or data area for destination exceeded.
Page 294 Section 5-19 Conversion Instructions integer. If the results is less than 0000, then 0000 is written to R, and if the result is greater than 9999, then 9999 is written to R. The following table shows the functions and ranges of the parameter words:...
Page 295: Signed Binary To Bcd Scaling - Scl2
If the result is negative, then CY is set to 1. If the result is less than –9999, then –9999 is written to R. If the result is greater than 9999, then 9999 is writ- ten to R.
Page 296 When 05000 is turned ON in the following example, the signed binary source data in 001 (#FFE2) is converted to BCD according to the parameters in DM 0000 to DM 0002. The result (#0018) is then written to LR 00 and CY is turned ON because the result is negative.
Page 297: Bcd To Signed Binary Scaling - Scl3
Parameter words P1+3 and P1+4 define upper and lower limits for the result. If the result is greater than the upper limit in P1+3, then the upper limit is writ- ten to R. If the result is less than the lower limit in P1+4, then the lower limit is written to R.
Page 298 ON when the result, R, is 0000. Example The status of 00101 determines the sign of the BCD source word in the follow- ing example. If 00101 is ON, then the source word is negative. When 00100 is turned ON, the BCD source data in LR 02 is converted to signed binary according to the parameters in DM 0000 to DM 0004.
Page 299: Hours-To-Seconds - Sec
Section 5-19 Conversion Instructions 1035 is less than the lower limit specified in DM 0004, so the lower limit is writ- ten to DM 0100.) 25313 (Always ON) Address Instruction Operands CLC(41) 00000 25313 00001 CLC(41) 00101 00002 00101 STC(40)
Page 300: Seconds-To-Hours - Hms(--)
This instruction is available in the CQM1 only. S and S+1 must be within the same data area. R and R+1 must be within the same data area. S and S+1 must be BCD and must be between 0 and 35,999,999 seconds.
Page 301: Column-To-Line - Line
(S to S+15) to the 16 bits of word D (00 to 15). 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1...
Page 302: Line-To-Column - Colm
C, of the 16-word set (D to D+15). 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1...
Page 303: 2'S Complement - Neg(--)
ON when the content of S is zero; otherwise OFF. Example The following example shows how to use COLM(––) to move the contents of word DM 0100 (00 to 15) to bit column 15 of the set (DM 0200 to DM 0215). 00000 Address Instruction Operands COLM(––)
Page 304: Double 2'S Complement - Negl(--)
S+1 from $0000 0000 and outputting the result to R and R+1; it will calcu- late the absolute value of negative signed binary data. If the content of S is 0000 0000, the content of R will also be 0000 0000 after execution and EQ (SR 25506) will be turned on.
Page 305 Conversion Instructions Example The following example shows how to use NEGL(––) to find the 2’s comple- ment of the hexadecimal value in IR 151, IR 150 (001F FFFF) and output the result to HR 04, HR 03. 00000 Address Instruction Operands NEGL(––)
Page 306: Bcd Calculation Instructions
When the execution condition is OFF, ADD(30) is not executed. When the execution condition is ON, ADD(30) adds the contents of Au, Ad, and CY, and places the result in R. CY will be set if the result is greater than 9999. Au + Ad + CY Flags Au and/or Ad is not BCD.
Page 307: Bcd Subtract - Sub(31)
ON, SUB(31) subtracts the contents of Su and CY from Mi, and places the result in R. If the result is negative, CY is set and the 10’s com- plement of the actual result is placed in R. To convert the 10’s complement to the true result, subtract the content of R from zero (see example below).
Page 308 When 00002 is ON, the following ladder program clears CY, subtracts the con- tents of DM 0100 and CY from the content of 010 and places the result in HR If CY is set by executing SUB(31), the result in HR 10 is subtracted from zero (note that CLC(41) is again required to obtain an accurate result), the result is placed back in HR 10, and HR 1100 is turned ON to indicate a negative result.
Page 309: Bcd Multiply - Mul(32)
HR 10 2423 (0000 + (10000 – 7577)) CY 1 (negative result) In the above case, the program would turn ON HR 1100 to indicate that the value held in HR 10 is negative. 5-20-5 BCD MULTIPLY – MUL(32) Operand Data Areas...
Page 310: Bcd Divide - Div(33)
IR, SR, AR, DM, HR, TC, LR, # R: First result word (BCD) IR, SR, AR, DM, HR, LR Limitations R and R+1 must be in the same data area. DM 6143 to DM 6655 cannot be used for R.
Page 311: Double Bcd Add - Addl(54)
When the execution condition is OFF, DIV(33) is not executed and the pro- gram moves to the next instruction. When the execution condition is ON, Dd is divided by Dr and the result is placed in R and R + 1: the quotient in R and the remainder in R + 1.
Page 312 The rightmost 8 digits of the two numbers are added using ADDL(54), i.e., the contents of LR 00 and LR 01 are added to DM 0010 and DM 0011 and the results is placed in HR 10 and HR 11. The second addition adds the leftmost 4 digits of each number using ADD(30), and includes any carry from the first addition.
Page 313: Double Bcd Subtract - Subl(55)
ON, SUBL(55) subtracts CY and the 8-digit contents of Su and Su+1 from the 8-digit value in Mi and Mi+1, and places the result in R and R+1. If the result is negative, CY is set and the 10’s complement of the actual result is placed in R.
Page 314 The following example works much like that for single-word subtraction. In this example, however, BSET(71) is required to clear the content of DM 0000 and DM 0001 so that a negative result can be subtracted from 0 (inputting an 8- digit constant is not possible).
Page 315: Double Bcd Multiply - Mull(56)
When the execution condition is OFF, MULL(56) is not executed. When the execution condition is ON, MULL(56) multiplies the eight-digit content of Md and Md+1 by the content of Mr and Mr+1, and places the result in R to R+3. Md + 1...
Page 316: Square Root - Root(72)
Section 5-20 BCD Calculation Instructions divided by the content of Dr and Dr+1 and the result is placed in R to R+3: the quotient in R and R+1, the remainder in R+2 and R+3. Remainder Quotient Dr+1 Dd+1 Flags Dr and Dr+1 contain 0.
Page 317: Binary Calculation Instructions
When the execution condition is OFF, ADB(50) is not executed. When the exe- cution condition is ON, ADB(50) adds the contents of Au, Ad, and CY, and places the result in R. CY will be set if the result is greater than FFFF. Au + Ad + CY ADB(50) can also be used to add signed binary data.
Page 318: Binary Subtract - Sbb(51)
HR 11 = R+1 00001 In the case below, A6E2 + 80C5 = 127A7. The result is a 5-digit number, so CY (SR 25504) = 1, and the content of R + 1 becomes #0001. Au: IR 010 Ad: DM 0100...
Page 319: Sbb(51)
Section 5-21 Binary Calculation Instructions and places the result in R. If the result is negative, CY is set and the 2’s com- plement of the actual result is placed in R. Mi – Su – CY SBB(51) can also be used to subtract signed binary data. With CQM1-...
Page 320: Binary Multiply - Mlb(52)
When the execution condition is OFF, MLB(52) is not executed. When the exe- cution condition is ON, MLB(52) multiplies the content of Md by the contents of Mr, places the rightmost four digits of the result in R, and places the left- most four digits in R+1.
Page 321: Double Binary Add - Adbl
Section 5-21 Binary Calculation Instructions of Dr and the result is placed in R and R+1: the quotient in R, the remainder in R+1. Quotient Remainder R + 1 Flags Dr contains 0. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.)
Page 322: Double Binary Subtract - Sbbl
IR, SR, AR, DM, HR, LR Limitations This instruction is available in the CQM1-CPU4@-E/-EV1 only. Mi and Mi+1 must be in the same data area, as must Su and Su+1, and R and R+1. DM 6142 to DM 6655 cannot be used for R.
Page 323 Section 5-21 Binary Calculation Instructions actual result is placed in R+1 and R. Use NEGL(––) to convert the 2’s comple- ment to the true result. Mi + 1 Su + 1 – R + 1 SBBL(––) can also be used to subtract signed binary data. The underflow and overflow flags (SR 25404 and SR 25405) indicate whether the result has exceeded the lower or upper limits of the 32-bit signed binary data range.
Page 324: Signed Binary Multiply - Mbs
MBS(––) multiplies the signed binary content of two words and outputs the 8- digit signed binary result to R+1 and R. The rightmost four digits of the result are placed in R, and the leftmost four digits are placed in R+1.
Page 325: Double Signed Binary Multiply - Mbsl
In the following example, MBSL(––) is used to multiply the signed binary con- tents of IR 101 and IR 100 with the signed binary contents of DM 0021 and DM 0020 and output the result to LR 24 through LR 01.
Page 326: Signed Binary Divide - Dbs
Description DBS(––) divides the signed binary content of Dd by the signed binary content of Dr, and outputs the 8-digit signed binary result to R+1 and R. The quotient is placed in R, and the remainder is placed in R+1.
Page 327: Double Signed Binary Divide - Dbsl
DBS(––) divides the 32-bit (8-digit) signed binary data in Dd+1 and Dd by the 32-bit signed binary data in Dr+1 and Dr, and outputs the 16-digit signed binary result to R+3 through R. The quotient is placed in R+1 and R, and the remainder is placed in R+3 and R+2.
Page 328: Special Math Instructions
D+1. The address is identified differently for the DM area: 1,2,3... 1. For an address in the DM area, the word address is written to C+1. For ex- ample, if the address containing the maximum value is DM 0114, then #0114 is written in D+1.
Page 329: Find Minimum - Min
Section 5-22 Special Math Instructions !Caution If bit 14 of C is ON, values above #8000 are treated as negative numbers, so the results will differ depending on the specified data type. Be sure that the correct data type is specified.
Page 330: Average Value - Avg
Signed binary 0 (OFF): Unsigned binary !Caution If bit 14 of C is ON, values above #8000 are treated as negative numbers, so the results will differ depending on the specified data type. Be sure that the correct data type is specified.
Page 331 Content of S from the N execution of AVG(––) Precautions The average value is calculated in binary. Be sure that the content of S is in binary. N must be BCD from #0001 to #0064. If the content of N #0065, AVG(––)
Page 332: Sum - Sum
The 3 rightmost digits of C must be BCD between 001 and 999. DM 6143 to DM 6655 cannot be used for D. If bit 14 of C is OFF (setting for BCD data), all data within the range R +N–1 must be BCD.
Page 333 Special Math Instructions Addition Units Words will be added if bit 13 is OFF and bytes will be added if bit 13 is ON. If bytes are specified, the range can begin with the leftmost or rightmost byte of R .
Page 334: Arithmetic Process - Apr
When the execution condition is OFF, APR(––) is not executed. When the exe- cution condition is ON, the operation of APR(––) depends on the control word If C is #0000 or #0001, APR(––) computes sin( ) or cos( )*. The BCD value of S specifies in tenths of degrees.
Page 335 The content of word C specifies the number of line segments in the approxi- mation, and whether the input and output are in BCD or BIN form. Bits 00 to 07 contain the number of line segments less 1, m–1, as binary data. Bits 14 and 15 determine, respectively, the output and input forms: 0 specifies BCD and 1 specifies BIN.
Page 336 Section 5-22 Special Math Instructions If bit 13 of C is set to 1, the graph will be reflected from left to right, as shown in the following diagram. The following example demonstrates the construction of a linear approxima- tion with 12 line segments. The block of data is continuous, as it must be, from DM 0000 to DM 0026 (C to C + (2 12 + 2)).
Page 337: Logic Instructions
Description When the execution condition is OFF, COM(29) is not executed. When the execution condition is ON, COM(29) clears all ON bits and sets all OFF bits in Precautions The complement of Wd will be calculated every cycle if the undifferentiated form of COM(29) is used.
Page 338: Logical Or - Orw(35)
DM 6144 to DM 6655 cannot be used for R. Description When the execution condition is OFF, ORW(35) is not executed. When the execution condition is ON, ORW(35) logically OR’s the contents of I1 and I2 bit-by-bit and places the result in R. Example Indirectly addressed DM word is non-existent.
Page 339: Exclusive Or - Xorw(36)
DM 6144 to DM 6655 cannot be used for R. Description When the execution condition is OFF, XORW(36) is not executed. When the execution condition is ON, XORW(36) exclusively OR’s the contents of I1 and I2 bit-by-bit and places the result in R.
Page 340: Increment/Decrement Instructions
Limitations DM 6144 to DM 6655 cannot be used for Wd. Description When the execution condition is OFF, INC(38) is not executed. When the exe- cution condition is ON, INC(38) increments Wd, without affecting Carry (CY). Precautions The content of Wd will be incremented every cycle if the undifferentiated form of INC(38) is used.
Page 341 Section 5-24 Increment/Decrement Instructions DEC(39) works the same way as INC(38) except that it decrements the value instead of incrementing it. Precautions The content of Wd will be decremented every cycle if the undifferentiated form of DEC(39) is used. Use the differentiated form (@DEC(39)) or combine DEC(39) with DIFU(13) or DIFD(14) to decrement Wd just once.
Page 342: Subroutine Instructions
The instructions within a subroutine are written in the same way as main program code. When all the subroutine instructions have been executed, control returns to the main program to the point just after the point from which the subroutine was entered (unless otherwise specified in the subroutine).
Page 343 RET(93) END(01) Flags A subroutine does not exist for the specified subroutine number. A subroutine has called itself. An active subroutine has been called. !Caution SBS(91) will not be executed and the subroutine will not be called when ER is...
Page 344: Special Instructions
TRSM(45) and gives an example program. Ladder Symbol TRSM(45) Description TRSM(45) is used in the program to mark locations where specified data is to be stored in Trace Memory. Up to 12 bits and up to 3 words may be desig-...
Page 345 TRSM(45) is not controlled by an execution condition, but rather by two bits in the AR area: AR 2515 and AR 2514. AR 2515 is the Sampling Start bit. This bit is turned ON to start the sampling processes for tracing. The Sampling Start bit must not be turned ON from the program, i.e., it must be turned ON...
Page 346: Message Display - Msg(46)
Appendix H for the ASCII codes. Japanese katakana characters are included in this code. If not all eight words are required for the message, it can be stopped at any point by inputting “OD.” When OD is encountered in a message, no more words will be read and the words that normally would be used for the mes- sage can be used for other purposes.
Page 347: I/O Refresh - Iorf(97)
To refresh I/O words, specify the first (St) and last (E) I/O words to be refreshed. When the execution condition for IORF(97) is ON, all words between St and E will be refreshed. This will be in addition to the normal I/O refresh performed during the CPU Unit’s cycle.
Page 348: Macro - Mcro(99)
ON, MCRO(99) copies the contents of I1 to I1+3 to IR 096 to IR 099, copies the contents of O1 to O1+3 to IR 196 to IR 199, and then calls and executes the subroutine specified in N. When the subroutine is completed, the contents of IR 196 through IR 199 is then transferred back to O1 to O1+3 before MCRO(99) is completed.
Page 349: Bit Counter - Bcnt(67)
ON in all words between SB and SB+(N–1) and places the result in R. Flags N is not BCD, or N is 0; SB and SB+(N–1) are not in the same area. The resulting count value exceeds 9999. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.)
Page 350 12 is ON. MSB LSB When bit 12 is OFF the bytes will be ORed in this order: 1, 2, 3, 4, ..When bit 12 is ON the bytes will be ORed in this order: 2, 3, 4, 5, ..
Page 351: Failure Point Detection - Fpd
Limitations This instruction is available in the CQM1 only. D and D+8 must be in the same data area when bit 15 of C is ON. DM 6144 to DM 6655 cannot be used for T or D. C must be input as a constant.
Page 352 CY Flag if desired. 4. If bit 15 of C is ON, a preset message with up to 8 ASCII characters will be displayed on the Peripheral Device along with the bit address mentioned in step 2.
Page 353 Bit number Timer or counter number Note a) *For the TC area, bit 09 of D+1 indicates whether the number is a timer or counter. A 0 indicates a timer, and a 1 indicates a counter. b) The status of the leftmost bit of the bit number (bit 03) is reversed.
Page 354 FPD(––) is executed and begins monitoring when LR 0000 goes ON. If LR 0015 does not turn ON within 123.4 s and IR 10000 through IR 10003 are all ON, IR 10002 will be selected as the cause of the error, an FAL(06) error will be generated with an FAL number of 10, and the bit address and preset mes- sage (“10002–1ABC”) will be displayed on the Peripheral Device.
Page 355: Interrupt Control - Int(89)
ON, INT(89) is used to control interrupts and performs one of the six functions shown in the following table depending on the value of CC. Note Refer to 1-5 CQM1 Interrupt Functions and 1-6 CPM1/CPM1A Interrupt Func- tions for more details.
Page 356 Set the corresponding bit in D to 1 to clear an I/O interrupt input. Bits 00 to 03 correspond to 00000 to 00003 (00003 to 00006 in CPM1/CPM1A PCs). Bits 04 to 15 should be set to 0.
Page 357: Set Pulses - Puls(65)
Section 5-26 Special Instructions ing bit in D to 1 in order to renew the input’s counter SV. (Bits 00 to 03 corre- spond to 00000 to 00003 in CQM1 PCs, 00003 to 00006 in CPM1/CPM1A PCs.) CQM1 PCs Word D bits: 3 2 1 0...
Page 358 Port Specifier (P) The port specifier indicates the pulse output location. The parameters set by the in C and N will apply to the next SPED(64) or ACC(––) instruction in which the same port output location is specified. Pulse output location...
Page 359: Speed Output- Sped(64)
Output bits IR 10000 to IR 10015. The first two digits of P specify which bit of IR 100 is the output bit and the third digit of P is always set to 0. For example, P=000 specifies IR 10000, P=010 specifies IR 10001, ...
Page 360 Special Instructions In independent mode, the number of pulses that have been output to ports 1 and 2 are contained in IR 236 and 237 (port 1) and IR 238 and IR 239 (port 2). Leftmost 4 digits Rightmost 4 digits...
Page 361: Pulse Output - Pls2
The pulse output cannot be used when interval timer 0 is operating. When a pulse output with a frequency of 500 Hz or higher is output from an output bit, set interrupt processing for the TIMH(15) TC numbers 000 to 003 by setting #0104 in DM 6629 of the PC Setup.
Page 362 The content of C determines the acceleration/deceleration rate. During accel- eration or deceleration, the output frequency is increased or decreased by the amount set in C every 4.08 ms. C must be BCD from 0001 to 0200 (10 Hz to 2 kHz).
Page 363: Acceleration Control - Acc
M always specifies the mode. Set P=001 or 002 to indicate port 1 or 2. Set M=000 to 003 to indicate modes 0 to Note Refer to 1-3 Pulse Output Function (CQM1 Only) for more details.
Page 364 Special Instructions Mode 0 (M=000) Mode 0 is used to output a specified number of CW or CCW pulses from port 1 or 2. The acceleration rate, frequency after acceleration, deceleration point, deceleration rate, and frequency after deceleration can all be controlled.
Page 365 1,2,3... 1. The content of C determines the acceleration rate. During acceleration, the output frequency is increased by the amount set in C every 4.08 ms. C must be BCD from 0001 to 0200 (10 Hz to 2 kHz). 2. The content of C+1 specifies the target frequency. C+1 must be BCD from 0000 to 5000 (0 Hz to 50 kHz).
Page 366: Pulse With Variable Duty Ratio - Pwm
DM 6643 to 1 to enable variable duty ratio pulse output from port 1, and set the leftmost digit of DM 6644 to 1 to enable variable duty ratio pulse output from port 2. It is not possible to output normal pulses from a port that is set for variable duty ratio output.
Page 367: Data Search - Srch
C+1. The address is identified differently for the DM area: 1,2,3... 1. For an address in the DM area, the word address is written to C+1. For ex- ample, if the lowest address containing the comparison data is DM 0114, then #0114 is written in C+1.
Page 368: Pid Control - Pid
PID(––) performs PID control based on the parameters specified in P1 through P1+6. The data in IW is used to calculate the output data that is writ- ten to OW. The following table shows the function of the parameter words.
Page 369 Determines the strength of the input filter. The lower the coefficient, the weaker the filter. This setting must be BCD from 100 to 199, or 000. A setting of 000 sets the default value (0.65) and a setting of 100 to 199 sets the coefficient from 0.00 to 0.99.
Page 370: Communications Instructions
D and D+(N 2)–1 must be in the same data area. DM 6144 to DM 6655 cannot be used for D or N. N must be BCD from #0000 to #0256. (#0000 to #0061 in host link mode) Description When the execution condition is OFF, RXD(47) is not executed. When the...
Page 371: Transmit - Txd(48)
Section 5-27 Communications Instructions The order in which data is written to memory depends on the value of digit 0 of C. Eight bytes of data 12345678... will be written in the following manner: Digit 0 = 0 Digit 0 = 1...
Page 372 PC Setup, etc. Host Link Mode N must be BCD from #0000 to #0061 (i.e., up to 122 bytes of ASCII). The value of the control word determines the port from which data will be output, as shown below.
Page 373: Change Rs-232C Setup - Stup
MSB LSB When digit 0 of C is 0, the bytes of source data shown above will be transmit- ted in this order: 12345678... When digit 0 of C is 1, the bytes of source data shown above will be transmit- ted in this order: 21436587...
Page 374 Communications Board port B (PC Setup: DM 6550 to DM 6554) If S is a word address, the contents of S through S+4 are copied to the 5 words in the PC Setup that contain the settings for the port specified by N.
Page 375: Advanced I/O Instructions
Different from Output Unit 0007 If there are 8 digits of source data, they are placed in S and S+1, with the most significant digits placed in S+1. If there are 4 digits of source data, they are placed in S.
Page 376: Digital Switch Input - Dsw(87)
IW and places the result in R. If the value is an 8-digit number, it is placed in R and R+1, with the most signif- icant digits placed in R+1. The number of digits is set in DM 6639 of the PC Setup.
Page 377: Ten Key Input - Tky(18)
D+1 is lost. 2. The bits of D+2 and bit 4 of OW indicate key input. When one of the keys on the keypad (0 to F) is being pressed, the corresponding bit in D+2 (00 to 15) and bit 4 of OW are turned ON.
Page 378 Section 5-28 Advanced I/O Instructions Indirectly addressed DM word is non-existent. (Content of *DM word Flags is not BCD, or the DM area boundary has been exceeded.) and D +1 are not in the same data area.
Page 380: Host Link Commands
Communications Procedure ........
Page 381: Communications Procedure
Section 6-1 Communications Procedure Command Chart The commands listed in the chart below can be used for host link communica- tions with the CQM1/CPM1/CPM1A/SRM1. These commands are all sent from the host computer to the PC. Header Name PC mode...
Page 382 The right to send a frame is called the “transmission right.” The Unit that has the transmission right is the one that can send a frame at any given time. The transmission right is traded back and forth between the host computer and the PC each time a frame is transmitted.
Page 383: Command And Response Formats
An “@” symbol must be placed at the beginning. Node No. Identifies the PC communicating with the host computer. Specify the node number set for the PC in the PC Setup (DM 6648, DM 6653). Header Code Set the 2-character command code.
Page 384 Section 6-2 Command and Response Formats sion is split, the ends of the first and intermediate frames are marked by a delimiter instead of a terminator. Dividing Commands (Host Computer to PC) As each frame is transmitted by the host computer, the computer waits for the delimiter to be transmitted from the PC.
Page 385 EXCLUSIVE OR performed on the data from the beginning of the frame until the end of the text in that frame (i.e., just before the FCS). Calcu- lating the FCS each time a frame is received and checking the result against the FCS that is included in the frame makes it possible to check for data errors in the frame.
Page 386 In host link communications, commands are ordinarily sent from the host computer to the PC, but it is also possible for commands to be sent from the PC to the host computer. In Host Link Mode, any data can be transmitted from the PC to the host computer.
Page 387: Host Link Commands
Beginning word* No. of words Terminator code (0000 to 0256) Note Beginning word: 0000 to 0255 in CQM1 PCs, 0000 to 0019 and 0200 to 0255 in CPM1/CPM1A/SRM1 PCs. Response Format An end code of 00 indicates normal completion. x 10...
Page 388 Note 1. Beginning word: 0000 to 0099 in CQM1 PCs, 0000 to 0019 in CPM1/ CPM1A/SRM1 PCs 2. No. of words: 0001 to 0100 in CQM1 PCs, 0001 to 0020 in CPM1/CPM1A/ SRM1 PCs Response Format An end code of 00 indicates normal completion.
Page 389 Terminator code (0001 to 6656) Note Beginning word: 0000 to 6655 in CQM1 PCs, 0000 to 1023 and 6144 to 6655 in CPM1/CPM1A PCs, and 0000 to 2047 and 6144 to 6655 in SRM1 PCs. Response Format An end code of 00 indicates normal completion.
Page 390 The contents of the number of words specified by the command are returned in hexadecimal as a response. The words are returned in order, starting with the specified beginning word. Note Be careful about the configuration of the DM area, as it varies depending on the CPU Unit model. 6-3-7 AR AREA READ ––...
Page 391 Parameters Write Data (Command) Specify in order the contents of the number of words to be written to the IR or SR area in hexadecimal, starting with the specified beginning word. Note If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed.
Page 392 Parameters Write Data (Command) Specify in order the contents of the number of words to be written to the HR area in hexadecimal, starting with the specified beginning word. Note If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed.
Page 393 Specify the status of the Completion Flags, for the number of timers/counters to be written, in order (from the beginning word) as ON (i.e., “1”) or OFF (i.e., “0”). When a Completion Flag is ON, it indicates that the time or count is up.
Page 394 Terminator code Note DM 1024 to DM 6143 in CPM1/CPM1A PCs and DM 2048 to DM 6143 in SRM1 PCs cannot be specified. If an attempt to write to any of these words is made, the writing operation will not be executed for these words and the com-...
Page 395 TC number in the user’s program and reads the PV, which assumed to be set as a constant. The SV that is read is a 4-digit decimal number (BCD). The program is searched from the beginning, which may take as much as 10 seconds to produce a response.
Page 396 Section 6-3 Host Link Commands 3. Use this command only when it is definite that a constant SV has been set. 4. The response end code will indicate an error (16) if the SV wasn’t entered as a constant. 6-3-16 SV READ 2 –– R$ Reads the constant SV or the word address where the SV is stored.
Page 397 Host Link Commands 6-3-17 SV READ 3 –– R% (CQM1 Only) Reads the constant SV or the word address where the SV is stored. The SV that is read is a 4-digit decimal number (BCD) written in the second word of the TIM, TIMH(15), CNT, or CNTR(12) instruction at the specified program address in the user’s program.
Page 398 Header Name TC number* SV (0000 to 9999) Terminator code Note TC number: 0000 to 0511 in CQM1 PCs, 0000 to 0127 in CPM1/CPM1A/ SRM1 PCs Response Format An end code of 00 indicates normal completion. x 10 x 10...
Page 399 End code Terminator code Parameters Name, TC Number (Command) In “Name,” specify the name of the instruction, in four characters, for changing the SV. In “TC number,” specify the timer/counter number used for the instruc- tion. Instruction name Classification (Space)
Page 400 End code Terminator code Parameters Name, TC Number (Command) In “Name,” specify the name of the instruction, in four characters, for changing the SV. In “TC number,” specify the timer/counter number used for the instruc- tion. Instruction name Classification TC number...
Page 401 4 Kbytes 8 Kbytes In CQM1 PCs, the “Message” parameter is a FAL/FALS number that exists when the command is executed. When there is no message, this parameter is omitted. In CPM1/CPM1A/SRM1 PCs, the “Message” parameter is a 16-character message that exists when the command is executed. When there is no mes- sage, this parameter is omitted.
Page 402 (2nd word) Parameters Error Clear (Command) Specify 01 to clear errors and 00 to not clear errors (BCD). Fatal errors can be cleared only when the PC is in PROGRAM mode. Error Information (Response) The error information comes in two words.
Page 403 ON: Cycle time overrun (Error code F8) 6-3-24 FORCED SET –– KS Force sets a bit in the IR, SR, LR, HR, AR, or TC area. Just one bit can be force set at a time. Once a bit has been forced set or reset, that status will be retained until a FORCED SET/RESET CANCEL (KC) command or the next FORCED SET/ RESET command is transmitted.
Page 404 6-3-25 FORCED RESET –– KR Force resets a bit in the IR, SR, LR, HR, AR, or TC area. Just one bit can be force reset at a time.
Page 405 In “Name,” specify the area (i.e., IR, SR, LR, HR, AR, or TC) that is to be forced reset. Specify the name in four characters. In “Word address,” specify the address of the word, and in “Bit” the number of the bit that is to be forced reset.
Page 406 Cancels all forced set and forced reset bits (including those set by FORCED SET, FORCED RESET, and MULTIPLE FORCED SET/RESET). If multiple bits are set, the forced status will be cancelled for all of them. It is not possible to cancel bits one by one using KC.
Page 407 Characters code Parameters Characters (Command, Response) For the command, this setting specifies any characters other than the carriage return (CHR$(13)). For the response, the same characters as specified by the command will be returned unaltered if the test is successful.
Page 408 Program data up to the maximum memory size. 6-3-32 COMPOUND COMMAND –– QQ Registers at the PC all of the bits, words, and timers/counters that are to be read, and reads the status of all of them as a batch.
Page 409 Read Word address, Data Format (Command) Depending on the area and type of data that are to be read, the information to be read is as shown in the following table. The “read data” is specified in four digits BCD, and the data format is specified in two digits BCD.
Page 410 (S): Space Data Break (Command) The read information is specified one item at a time separated by a break code (,). The maximum number of items that can be specified is 128. (When the PV of a timer/counter is specified, however, the status of the Completion Flag is also returned, and must therefore be counted as two items.)
Page 411 The INITIALIZE command does not use node numbers or FCS, and does not receive a response. Command Format 6-3-35 Undefined Command –– IC This response is returned if the header code of a command cannot be decoded. Check the header code. Response Format x 10 x 10 Node no.
Page 412: Pc Operations And Processing Time
CQM1 Cycle Time ........
Page 413: Cqm1 Cycle Time And I/O Response Time
CQM1 Cycle Time and I/O Response Time CQM1 Cycle Time and I/O Response Time 7-1-1 The CQM1 Cycle CQM1 Operation The overall flow of CQM1 operation is as shown in the following flowchart. Flowchart Power application Is DIP switch pin 2 set to...
Page 414 Cyclic refresh must be executed for both inputs and outputs. If input refresh is to be executed at the time of interrupts, then set the input refresh range in the PC Setup (DM 6630 to DM 6638). Stopping direct refresh can be set in DM 6639 of the PC Setup.
Page 415 Cycle time Operation conditions 10 ms or longer TIMH(15) may be inaccurate when TC 016 through TC 511 are used (operation will be normal for TC 000 through TC 015) (see note 1). 20 ms or longer Programming using the 0.02-second Clock Bit (SR 25401) may be inaccurate.
Page 416 The I/O response time is the time it takes after an input signal has been received (i.e., after an input bit has turned ON) for the PC to check and pro- cess the information and to output a control signal (i.e., to output the result of the processing to an output bit).
Page 417 One-to-one Link I/O Response Time When two CQM1s are linked one-to-one, the I/O response time is the time required for an input executed at one of the CQM1s to be output to the other CQM1 by means of one-to-one link communications.
Page 418 The CQM1 takes the longest to respond under the following circumstances: Time 1,2,3... 1. The CQM1 receives an input signal just after the input refresh phase of the cycle. 2. The master to slave transmission does not begin on time.
Page 419 Item Contents Time Interrupt input ON delay This is the delay time from the time the interrupt input bit turns ON 50 s until the time that the interrupt is executed. This is unrelated to other interrupts. (Interrupt condition realized.) (see note)
Page 420: Execution Times
140 s In addition to the response time shown above, the time required for executing the interrupt processing routine itself and a return time of 40 s must also be accounted for when returning to the process that was interrupted.
Page 421: Ld Not
LD NOT AND NOT OR NOT AND LD OR LD 0.75 Without direct outputs or for operands other than OUT NOT IR 10000 to IR 11515 when direct outputs are used. 1.25 Direct outputs RSET 1.25 Direct outputs Constant for SV *DM for SV 54.1...
Page 422 Section 7-1 CQM1 Cycle Time and I/O Response Time Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) WSFT 44.7 With 1-word shift register 77.0 With 10-word shift register With 1,024-word shift register using *DM 2.25 ms...
Page 423 Section 7-1 CQM1 Cycle Time and I/O Response Time Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) XNRW 41.9 Constant V word word 45.1 Word V word word *DM V *DM 114.1...
Page 424 When decoding word to word When decoding *DM to *DM 138.5 DIST 66.0 When setting a constant to a word + a word 69.3 When setting a word to a word + a word When setting *DM to *DM +*DM 144.3 101.0...
Page 425 Changing PV via *DM 182.2 56.4 Stopping pulse output via word Stopping pulse output via *DM 80.2 High-speed counters 1 and 2 or pulse output from ports 1 and 2: 296.8 Starting comparison via word Starting comparison via *DM 324.3 207.3...
Page 426 High-speed counter 0 or pulse output from an output bit: 91.5 Designating output via word Designating output via *DM 117.4 High-speed counters 1 and 2 or pulse output from ports 1 and 2: 229.3 Designating output via word (reading status) Designating output via *DM (reading status) 249.3 229.8...
Page 427 Range table in words Range table in *DM 1.11 ms High-speed counters 1 and 2 or pulse output from ports 1 and 2: 692.8 Target table with 1 target in words and start Target table with 1 target in *DM and start 721.8...
Page 428 Section 7-1 CQM1 Cycle Time and I/O Response Time Code Mnemonic ON execution Conditions OFF execution time ( s) time ( s) PULS Pulse output from an output bit: 109.0 Number of pulses specified by word Number of pulses specified by *DM 137.8...
Page 429 Word designation, no message, initial *DM designation, message, initial 312.0 SRCH 62.4 Searching word, results to word Searching 1,024 word via *DM, results to *DM 2.64 ms Searching 6,144 word via *DM, results to *DM 15.11 ms 56.1 Searching word, results to word Searching 999 words via *DM, results to *DM 2.56 ms...
Page 430 XFRB 35.3 Transferring 1 bit between words with a constant for control data 56.8 Transferring 1 bit between words with a word for control data Transferring 255 bits between *DM with *DM for control data 298.3 PLS2 821.7 Words for control words *DM for control words 849.0...
Page 431: Cpm1/Cpm1A Cycle Time And I/O Response Time
Section 7-2 CPM1/CPM1A Cycle Time and I/O Response Time CPM1/CPM1A Cycle Time and I/O Response Time 7-2-1 The CPM1/CPM1A Cycle The overall flow of CPM1/CPM1A operation is as shown in the following flow- chart. Power application Initialization processes Initialization Check hardware and Program Memory.
Page 432: Timh(15)
Cycle time Operation conditions 10 ms or longer TIMH(15) may be inaccurate when TC 004 through TC 127 are used (operation will be normal for TC 000 through TC 003). 20 ms or longer Programming using the 0.02-second Clock Bit (SR 25401) may be inaccurate.
Page 433 The I/O response time is the time it takes after an input signal has been received (i.e., after an input bit has turned ON) for the PC to check and pro- cess the information and to output a control signal (i.e., to output the result of the processing to an output bit).
Page 434 The CPM1/CPM1A takes longest to respond when it receives the input signal Time just after the input refresh phase of the cycle, as shown in the illustration below. In that case, a delay of approximately one cycle will occur. Input...
Page 435 Slave #1 Slave #2 Output OFF Slave #3 response time Slave Output point Maximum I/O response time = 8 + 10 x 2 + 12 x 3 + 15 x 3 + 10 = 119 (ms)
Page 436 Item Contents Time Interrupt ON delay This is the delay time from the time the interrupt input bit turns ON until the 100 s time that the interrupt is executed. This is unrelated to other interrupts. Wait for completion of This is the time during which interrupts are waiting until processing has been See below.
Page 437 CPM1/CPM1A Cycle Time and I/O Response Time In addition to the response time shown above, the time required for executing the interrupt processing routine itself and a return time of 30 s must also be accounted for when returning to the process that was interrupted.
Page 438 CPM1/CPM1A Cycle Time and I/O Response Time Section 7-2 Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) TIMH Reset 19.0 Regular execution, constant for SV 25.7 28.4 15.8 20.2 Interrupt execution, constant for SV Regular execution, *DM for SV 19.0...
Page 439 Section 7-2 CPM1/CPM1A Cycle Time and I/O Response Time Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) TIMH Reset 19.0 Regular execution, constant for SV 25.7 28.4 15.8 20.2 Interrupt execution, constant for SV Regular execution, *DM for SV 19.0...
Page 440 Section 7-2 CPM1/CPM1A Cycle Time and I/O Response Time Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) 27.1 Constant V word word 28.7 Word V word word *DM V *DM 70.7 XORW 27.1...
Page 441 Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) CTBL 106.3 Target table with 1 target in words and start Target table with 1 target in *DM and start 120.3 775.5 Target table with 16 targets in words and start Target table with 16 targets in *DM and start 799.5...
Page 442 When decoding word to word When decoding *DM to *DM 96.3 DIST 39.1 When setting a constant to a word + a word 40.9 When setting a word to a word + a word When setting *DM to *DM +*DM 84.7 63.4...
Page 443: Srm1 Cycle Time And I/O Response Time
Cycle time Cycle time processing Output re- freshing RS-232C servicing Service peripheral port. Note 1. The cycle time can be read using Peripheral Devices. 2. Cycle time maximum and current cycle time are stored in AR 14 and AR 15.
Page 444 Cycle time Operation conditions 10 ms or longer TIMH(15) may be inaccurate when TC 004 through TC 127 are used (operation will be normal for TC 000 through TC 003). 20 ms or longer Programming using the 0.02-second Clock Bit (SR 25401) may be inaccurate.
Page 445 4. When the peripheral port is used, there is no CompoBus/S end wait time as it is always 0 or less. 5. CompoBus/S end wait time = 0.8 – 0.18 – 0 – 0 = 0.62 (CompoBus/S com- munication response time – Overseeing – RS-232C port servicing time –...
Page 446 One-to-one Link I/O Response Time When two SRM1s are linked one-to-one, the I/O response time is the time required for an input executed at one of the SRM1s to be output to the other SRM1 by means of one-to-one link communications.
Page 447 Maximum I/O Response The SRM1 takes the longest to respond under the following circumstances: Time 1,2,3... 1. The SRM1 receives an input signal just after the I/O refresh phase of the cycle. 2. The Master’s communications servicing just misses the master-to-slave transmission.
Page 448 This is the time it takes to change processing to an interrupt. 15 s processing Return This is the time it takes, from execution of RET(93), to return to the process- 15 s ing that was interrupted. Mask Processing Interrupts are masked during processing of the operations described below.
Page 449 Section 7-3 SRM1 Cycle Time and I/O Response Time 7-3-6 SRM1 Instruction Execution Times The following table lists the execution times for SRM1 instructions. Basic Instructions Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s)
Page 450 Section 7-3 SRM1 Cycle Time and I/O Response Time Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) TIMH 10.3 Reset Regular execution, constant for SV 14.1 13.9 10.9 Interrupt execution, constant for SV 15.6...
Page 451 Section 7-3 SRM1 Cycle Time and I/O Response Time Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) 14.3 Constant V word word 15.2 Word V word word *DM V *DM 37.3 XORW 14.3...
Page 452 When decoding word to word When decoding *DM to *DM 49.9 DIST 21.3 When setting a constant to a word + a word 21.9 When setting a word to a word + a word When setting *DM to *DM +*DM 45.7 34.3...
Page 453 53.7 13.2 MCRO 26.8 With word-set I/O operands With *DM-set I/O operands 43.5 Note Those instructions marked with an asterisk are expansion instructions. Exchangeable Expansion Instructions Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) 43.6...
Page 454: Troubleshooting
Troubleshooting Flowcharts ........
Page 455: Introduction
Note In addition to the errors described above, communications errors can occur when the PC is part of a Host Link System. Refer to page 442 for details. Programming Console Operation Errors The following error messages may appear when performing operations on the Programming Console.
Page 456: Programming Errors
Check level 0 checks for type A, B, and C errors; check level 1, for type A and B errors; and check level 2, for type A errors only.
Page 457: User-Defined Errors
60 to 69, 87, 88, and 89) are not subject to program checks. Program checks also do not cover DM 1024 to DM 6143 for PCs that do not support this part of the DM area (e.g., CQM1-CPU11-E and CQM1-CPU21-E). Data will not be written even if these areas are specified and data read from these areas will always be “0000.”...
Page 458: Operating Errors
The FAL numbers can be set arbitrarily to indicate particular conditions. The same number cannot be used as both an FAL number and an FALS number. To clear an FAL error, correct the cause of the error, execute FAL 00, and then clear the error using the Programming Console.
Page 459 AR 1413 ON: The transfer destination is write-protected. If the PC is the destination, turn off the power to the PC, be sure that pin 1 of the CPU Unit’s DIP switch is OFF, clear the error, and transfer again.
Page 460 An error has been detected in the PC Setup. Check flags AR 1300 to AR 1302, and cor- rect as directed. AR 1300 ON: An incorrect setting was detected in the PC Setup (DM 6600 to DM 6614) when power was turned on.
Page 461 AR 1308 ON: An unspecified bit area exists in the user program. Check the program and correct errors. AR 1309 ON: An error has occurred in the flash memory. Since the number of writings to the flash memory has exceeded the specified level, replace the CPU Unit.
Page 462: Error Log
DM1020 DM1021 Error Log Storage Methods The error log storage method is set in the PC Setup (DM 6655). Set any of the following methods. 1,2,3... 1. You can store the most recent 10 error log records and discard older records.
Page 463: Host Link Errors
80: Fatal DM2020 DM2021 Error Log Storage The error log storage method is set in the PC Setup (DM 6655). Set any of the Methods following methods. 1,2,3... 1. You can store the most recent 7 error log records and discard older records.
Page 464 Transfer the command again. Power Interruptions The following responses may be received from the CQM1 if a power interrup- tion occurs, including momentary interruptions. If any of these responses are received during or after a power interruption, repeat the command.
Page 465: Troubleshooting Flowcharts
Check I/O. (See page 448.) normal? Normal Operating Not normal Check operating environment. (See page 450.) environment nor- mal? Normal Replace the CPU Unit. Note Always turn off the power to the PC before replacing Units, batteries, wiring, or cables.
Page 466 Not lit Is Power indicator lit? Replace the Power Supply Unit. Note The allowable voltage ranges for the CQM1 are as shown below. CQM1-PA203/PA206: 85 to 264 VAC CQM1-PD026: 20 to 28 VDC...
Page 467 Section 8-8 Troubleshooting Flowcharts Fatal Error Check The following flowchart can be used to troubleshoot fatal errors that occur while the Power indicator is lit. RUN indicator not lit. Is the ERR/ALM indicator lit? Determine the cause Is PC mode displayed...
Page 468 Non-fatal Error Check Although the PC will continue operating during non-fatal errors, the cause of the error should be determined and removed as quickly as possible to ensure proper operation. It may to necessary to stop PC operation to remove certain non-fatal errors.
Page 469 Disconnect the external wires and check the conductivity of each wire. Operation O.K.? Replace the Output Check output device Unit. SOL1. Note The CPM1 PC doesn’t have the IR 10500 output indicator. Substitute with one from IR 01000 to IR 01915.
Page 470 Is terminal O.K.? block making proper Operation contact? O.K.? Is input wiring correct? Check operation by using a dummy input signal to turn the input ON and OFF. Wire correctly. Tighten the terminal Replace terminal screws connector. Operation O.K.? Replace the Output Return to "start."...
Page 471 55 C? Is the ambient Consider using a temperature above heater. 0 C? Is the ambient humidity Consider using an between 10% and air conditioner. 90%? Install surge pro- tectors or other Is noise being...
Page 472: Programming Instructions
A PC instruction is input either by pressing the corresponding Programming Console key(s) (e.g., LD, AND, OR, NOT) or by using function codes. To input an instruction with its function code, press FUN, the function code, and then WRITE. Refer to the pages listed programming and instruction details.
Page 473 Converts binary data in source word into BCD, and outputs converted data to result word. (@)ASL ARITHMETIC SHIFT Shifts each bit in single word of data one bit to left, with CY. LEFT (@)ASR ARITHMETIC SHIFT Shifts each bit in single word of data one bit to right, with CY.
Page 474 MOVE DIGIT Moves hexadecimal content of specified four-bit source digit(s) to specified destination digit(s) for up to four digits. (@)SFTR REVERSIBLE SHIFT Shifts data in specified word or series of words to either left or REGISTER right. (@)TCMP TABLE COMPARE Compares four-digit hexadecimal value with values in table consisting of 16 words.
Page 475 MACRO Calls and executes a subroutine replacing I/O words. Expansion Instructions The following table shows the instructions that can be treated as expansion instructions. The default function codes are given for instructions that have codes assigned by default. Code Mnemonic...
Page 476 Rounds off to 4 digits past the decimal point. (@)COLM LINE TO COLUMN Copies the 16 bits from the specified word to a bit CQM1 column of 16 consecutive words. SIGNED BINARY COM- Compares two 16-bit (4-digit) signed binary val-...
Page 477 Changes the communications parameters in the SRM1 SETUP PC Setup for a specified port. (@)SUM SUM CALCULATE Computes the sum of the contents of the words in CQM1 the specified range of memory. (@)XFRB TRANSFER BITS Copies the status of up to 255 specified source CQM1 bits to the specified destination bits.
Page 478: Error And Arithmetic Flag Operation
Although ladder diagram instructions, TIM, and CNT are executed when ER is ON, other instructions with a vertical arrow under the ER column are not executed if ER is ON. All of the other flags in the following table will also not operate when ER is ON.
Page 479 Appendix B Error and Arithmetic Flag Operation Instructions 25503 (ER) 25504 (CY) 25505 (GR) 25506 (EQ) 25507 (LE) 25402 (N) Page MUL(32) Unaffected Unaffected Unaffected Unaffected DIV(33) ANDW(34) ORW(35) XORW(36) XNRW(37) INC(38) Unaffected DEC(39) STC(40) Unaffected Unaffected Unaffected Unaffected Unaffected...
Page 480 Unaffected HEX(––) AVG(––) Note 1. Only expansion instructions with default function numbers are applicable to the SRM1 PCs. 2. SR 25410 will be ON when DSW(87) is being executed. 3. SR 25409 will be ON when 7SEG(88) is being executed.
Page 481 Unaffected Unaffected Note 1. Depending on the calculation results, ADBL(––) and SBBL(––) may also affect the status of the over- flow and underflow flags (SR 25404 and SR 25405). 2. Depending on the conversion results, NEG(––) and NEGL(––) may also affect the status of the un-...
Page 482: Memory Areas
128 or IR 000 to IR 015 IR 00000 to IR 01515 CQM1-CPU11/21-E: Up to 8 words (128 bits) can be used for I/O bits. Up to 7 bits Units can be connected. CQM1-CPU4@-EV1: Up to 16 words Output area...
Page 483 Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. At least 2,720 bits can be used as work bits. The total number of bits that can be used depends on the configuration of the PC system.
Page 484 The error code (a 2-digit number) is stored here when an error occurs. The FAL number is stored here when FAL(06) or FALS(07) is executed. This word is reset (to 00) by exe- cuting a FAL 00 instruction or by clearing the error from a Peripheral Device.
Page 485 All force-set or force-reset bits will be cleared when the PC is switched to RUN mode (see note). This bit is turned ON and OFF from a peripheral device. A setting can be made in the PC Setup (DM 6601) to cause the status of this Bit to be retained even when pow- ering up.
Page 486 SR 25212 (I/O Hold Bit) This bit is turned ON and OFF from a peripheral device. A setting can be made in the PC Setup (DM 6601) to cause the status of this Bit to be retained even when pow- ering up.
Page 487 08 to 14 Not used. Pulse Output Status for Pulse Output Bit Specification 0: Stopped; 1: Output (This bit is supported only for CPU Units produced in or after April 1995 (Lot No.: **45)). AR 12 00 to 15 Not used.
Page 488 ON (i.e., set to automatically transfer the contents of the Memory Cassette at power- up.) Note With the LSS/SSS, clear the forced-set status to turn OFF these bits, which will not change even after the operation is complete. (If the Programming Console is being used, these bits will automatically turn...
Page 489 “0000” from a peripheral device. AR 24 Power-up PC Setup Error Flag Turns ON when there is an error in DM 6600 to DM 6614 (the part of the PC Setup area that is read at power-up). Start-up PC Setup Error Flag Turns ON when there is an error in DM 6615 to DM 6644 (the part of the PC Setup area that is read at the beginning of operation).
Page 490 PC operation. Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. The contents of the HR area, Counter area, and read/write DM area are backed up by a capacitor. At 25 C, the capacitor will back up memory for 20 days.
Page 491 Appendix C Memory Areas 5. The contents of the HR area, LR area, Counter area, and read/write DM area are backed up by a capacitor. The backup time varies with the ambient temperature, but at 25 C, the capacitor will back up memory for 20 days.
Page 492 ON: The status of bits that are forced set/reset are maintained when switching between PROGRAM mode and MONITOR mode. The status of this bit can be maintained when PC power turns off by using the PC Setup. I/O Hold Bit (See note.) OFF: IR and LR bits are reset when starting or stopping operation.
Page 493 Not used. Note DM 6601 in the PC Setup can be set to maintain the previous status of the I/O Hold Bit (SR 25212) and the I/O Hold Bit (SR 25212) when power is turned off. If power is left OFF for longer than the backup time, however, status may be cleared.
Page 494 Not used. AR 13 Power-up PC Setup Error Flag Turns ON when there is an error in DM 6600 to DM 6614 (the part of the PC Setup area that is read at power-up). Start-up PC Setup Error Flag Turns ON when there is an error in DM 6615 to DM 6644 (the part of the PC Setup area that is read at the beginning of operation).
Page 495 2. Areas that cannot be used are cleared when the power is turned on. 3. The contents of AR 10 is backed up by the built-in capacitor. If power is left OFF for longer than the backup time, however, the contents may be cleared. For details regarding the backup time, refer to the CPM1A or CPM1 Operation Manual.
Page 496 PC operation. Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. The contents of the HR area, LR area, Counter area, and read/write DM area are backed up by a capacitor.
Page 497 00 to 07 FAL Error Code The error code (a 2-digit number) is stored here when an error occurs. The FAL number is stored here when FAL(06) or FALS(07) is executed. This word is reset (to 00) by execut- ing a FAL 00 instruction or by clearing the error from a Peripheral Device.
Page 498 08 to 15 Not used. AR Area These bits mainly serve as flags related to SRM1 operation. These bits retain their status even after the SRM1 power supply has been turned off or when operation begins or stops. Word(s) Bit(s)
Page 499 Not used. AR 13 Power-up PC Setup Error Flag Turns ON when there is an error in DM 6600 to DM 6614 (the part of the PC Setup area that is read at power-up). Start-up PC Setup Error Flag Turns ON when there is an error in DM 6615 to DM 6644 (the part of the PC Setup area that is read at the beginning of operation).
Page 500: Using The Clock Function
It is also possible, by using AR 2113, to simply set the seconds to “00” without going through a complicated procedure. When AR 2113 is turned ON, the clock time will change as follows: If the seconds setting is from 00 to 29, the seconds will be reset to “00” and the minute setting will remain the same.
Page 502: I/O Assignment Sheet
Appendix E I/O Assignment Sheet Name of system Produced by Verified by Authorized by PC model Sheet no. IR_____ Unit no.: Model: IR_____ Unit no.: Model: IR_____ Unit no.: Model: IR_____ Unit no.: Model:...
Page 504: Program Coding Sheet
Appendix F Program Coding Sheet Name of system Produced by Verified by Authorized by Chart no. Address Instruction Function Operands code...
Page 505 Appendix F Program Coding Sheet Address Instruction Function Operands code...
Page 506 Appendix F Program Coding Sheet Address Instruction Function Operands code...
Page 508: List Of Fal Numbers
Appendix G List of FAL Numbers Name of system Produced by Verified by Authorized by PC model Chart no. FAL contents Corrective measure FAL contents Corrective measure...
Page 509 Appendix G List of FAL Numbers FAL contents Corrective measure FAL contents Corrective measure...
Page 510: Extended Ascii
Appendix H Extended ASCII The following codes are used to output characters to the Programming Console or Data Access Console using MSG(46) or FPD(––). Refer to pages 325 and 330 for details. Right Left digit digit 0, 1, 8, 9 ”...
Page 512: Cpm1/Cpm1A And Cqm1 Memory Area Comparison
Appendix I CPM1/CPM1A and CQM1 Memory Area Comparison This table shows the differences between the CPM1/CPM1A and CQM1 memory areas. Data area CPM1/CPM1A CQM1 IR area Input area IR 000 to IR 009 IR 000 to IR 015 Output area...
Page 514: Glossary
AUTOEXEC.BAT An MS DOS file containing commands automatically executed at startup. back-up A copy made of existing data to ensure that the data will not be lost even if the original data is corrupted or erased. basic instruction A fundamental instruction used in a ladder diagram. See advanced instruction.
Page 515 Glossary bit designator An operand that is used to designate the bit or bits of a word to be used by an instruction. bit number A number that indicates the location of a bit within a word. Bit 00 is the rightmost (least-significant) bit;...
Page 516 An operand that specifies how an instruction is to be executed. The control data may specify the part of a word is to be used as the operand, it may specify the destination for a data transfer instructions, it may specify the size of a data table used in an instruction, etc.
Page 517 A unit of storage in memory that consists of four bits. digit designator An operand that is used to designate the digit or digits of a word to be used by an instruction. DIN track A rail designed to fit into grooves on various devices to allow the devices to be...
Page 518 `distributed’ over the system. Distributed control is a concept basic to PC Systems. DM area A data area used to hold only word data. Words in the DM area cannot be ac- cessed bit by bit. DM word A word in the DM area.
Page 519 Each group of four binary bits is numerically equivalent to one hexadecimal digit. host computer A computer that is used to transfer data to or receive data from a PC in a Host Link system. The host computer is used for data management and overall sys- tem control.
Page 520 I/O Units include Input Units and Output Units, each of which is avail- able in a range of specifications. I/O word A word in the IR area that is allocated to a Unit in the PC System and is used to hold I/O status for that Unit. IBM PC/AT or compatible A computer that has similar architecture to, that is logically compatible with, and that can run software designed for an IBM PC/AT computer.
Page 521 A type of programming where execution moves directly from one point in a pro- gram to another, without sequentially executing any instructions in between. jump number A definer used with a jump that defines the points from and to which a jump is to be made. ladder diagram (program) A form of program arising out of relay-based control systems that uses circuit- type diagrams to represent the logic flow of programming instructions.
Page 522 Acronym for light-emitting diode; a device used as for indicators or displays. leftmost (bit/word) The highest numbered bits of a group of bits, generally of an entire word, or the highest numbered words of a group of words. These bits/words are often called most-significant bits/words.
Page 523 NOT indicates an AND operation with the opposite of the actual status of the op- erand bit. The status of an input or output when a signal is said not to be present. The OFF state is generally represented by a low voltage or by non-conductivity, but can be defined as the opposite of either.
Page 524 The signal sent from the PC to an external device. The term output is often used abstractly or collectively to refer to outgoing signals. output bit A bit in the IR area that is allocated to hold the status to be sent to an output de- vice. output device An external device that receives signals from the PC System.
Page 525 The portable form of Programming Device for a PC. Programming Device A Peripheral Device used to input a program into a PC or to alter or monitor a program already held in the PC. There are dedicated programming devices, such as Programming Consoles, and there are non-dedicated devices, such as a host computer.
Page 526 A word in memory that is reserved for a special purpose and cannot be accessed by the user. reset The process of turning a bit or signal OFF or of changing the present value of a timer or counter to its set value or to zero. response code A code sent with the response to a data transmission that specifies how the transmitted data was processed.
Page 527 One or more words in which data is shifted a specified number of units to the right or left in bit, digit, or word units. In a rotate register, data shifted out one end is shifted back into the other end. In other shift registers, new data (either spec- ified data, zero(s) or one(s)) is shifted into one end and the data shifted out at the other end is lost.
Page 528 Operating environment settings for a Programming Device, e.g., the LSS or SSS. terminal instruction An instruction placed on the right side of a ladder diagram that uses the final ex- ecution conditions of an instruction line. timer A location in memory accessed through a TIM/CNT bit and used to time down from the timer’s set value.
Page 529 A switch used to write-protect the contents of a storage device, e.g., a floppy disk. If the hole on the upper left of a floppy disk is open, the information on this floppy disk cannot be altered.
Page 530: Index
– reversible counters ACC(– –) CTBL(63) ADBL(– –) cycle monitor time address tracing PC Setup settings See also tracing, data tracing. cycle time (CPM1/CPM1A) advanced I/O instructions calculating 7-SEGMENT DISPLAY OUTPUT effects on operations DIGITAL SWITCH INPUT processes functions...
Page 531 PC transmission other procedures programming procedures (CQM1) Programming Console operations See also host link commands programming messages data transfer resetting dividing frames types end codes user-defined errors frame definition execution condition maximum size...
Page 532 Index combining with OR AND LD combining with OR LD use in logic blocks AND NOT ANDW(34) ASC(86) ASFT(17) ASL(25) ASR(26) AVG(– –) I/O bits BCD(24) CPM1/CPM1A BCDL(59) CQM1 BCMP(68) SRM1 BCNT(67) I/O points BIN(23) BINL(58) refreshing BSET(71) I/O refresh operations...
Page 533 SCL(66) INT(89) SCL2(– –) IORF(97) SCL3(– –) JME(05) SDEC(78) – JMP(04) JMP(04) and JME(05) SFT(10) KEEP(11) SFTR(84) in controlling bit status SLD(74) ladder instructions SNXT(09) – SPED(64) LD NOT SRCH(– –) MAX(– –) SRD(75) MBS(– –) STC(40) MBSL(– –) STEP(08) MCMP(19) STH(–...
Page 534 (CPM1/CPM1A) – using SET and RSET counter mode – converting to mnemonic code high-speed counter display via GPC, FIT, LSS, or SSS overflows and overflows instructions input interrupt mode combining input interrupts AND LD and OR LD, 166 interval timers...
Page 535: Msg(46)
CPM1/CPM1A cycle time reading data effects on CQM1 cycle time reading with peripherals effects on SRM1 cycle time required EEPROMs SRM1 internal processing storing DM and UM data (CQM1 only) flowchart types output bit writing data controlling ON/OFF time messages...
Page 536: Ret(93)
PRV(62) defaults – PULS(65) expansion instructions I/O operations pulse outputs port servicing scan time determining status of ports 1 and 2 pulse output word from an output point interrupts from ports 1 and 2 external sources (CQM1) variable-duty-ratio parameters (CQM1)
Page 537 SRM1 See also instruction interrupt processing CPM1/CPM1A CQM1 SRM1 special instructions CPM1/CPM1A CQM1 SRM1 SRM1 cycle time TR bits use in branching tracing See also See data tracing and address tracing. troubleshooting TXD(48) write protecting the program PC Setup settings...
Page 538: Revision History
Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W228-E1-08 Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version.
Page 539 Revision code Date Revised content June 1997 The manual was revised to include the new CPM1A and SRM1 PCs and the V1 CQM1 CPU Units. The LSS was removed from the manual. Page 54: Note added. Page 105: CLC was added to program.
Page 540 Regional Headquarters OMRON EUROPE B.V. Wegalaan 67-69, NL-2132 JD Hoofddorp The Netherlands Tel: (31)2356-81-300/Fax: (31)2356-81-388 OMRON ELECTRONICS LLC 1 East Commerce Drive, Schaumburg, IL 60173 U.S.A. Tel: (1)847-843-7900/Fax: (1)847-843-8568 OMRON ASIA PACIFIC PTE. LTD. 83 Clemenceau Avenue, #11-01, UE Square,...
Page 541 Authorized Distributor: Cat. No. W228-E1-08 Note: Specifications subject to change without notice. Printed in Japan This manual is printed on 100% recycled paper.

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Omron CPM1 Programming Manual

Table of Contents

Precautions

Section 1 PC Setup and Other Features

Section 2 Special Features

Special Features

Memory Areas

Section 4 Ladder-Diagram Programming

Section 5 Instruction Set

Instruction Set

Host Link Commands

PC Operations and Processing Time

Troubleshooting

Glossary

Index

Revision History

Quick Links

Chapters

Troubleshooting

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Summary of Contents for Omron CPM1