Omron CQM1H - PROGRAM Programming Manual page 154

Absolute Encoder Interface Board
Origin Compensation
1,2,3...
Programming
Input Refresh Word Settings
DM 6634 contains the input refresh word settings for absolute high-speed
counter 1, and DM 6635 contains the settings for absolute high-speed counter
2. Make these settings when it is necessary to refresh inputs.
Number of words (2-digit BCD)
First word (2-digit BCD)
Default: 0000 (No inputs refreshed)
It is possible to compensate for a discrepancy between an absolute encoder's
origin and the actual origin. After origin compensation has been set, the data
from the absolute encoder will be adjusted before being output as the PV.
Once set, the origin compensation will remain in effect until the next origin
compensation is executed; it remains in effect even after power has been
turned OFF. Origin compensation can be set separately for ports 1 and 2.
The default setting is for no origin compensation.
Follow the procedure below to set origin compensation.
1. Set the absolute encoder to the desired origin location.
2. Make sure that pin 1 of the CQM1H CPU Unit's DIP switch is OFF (en-
abling Programming Devices to write DM 6144 through DM 6568), then
switch the PC to PROGRAM mode.
3. Set the absolute resolution in DM 6643 or DM 6644.
4. Make sure that a fatal error or FALS 9C error has not occurred.
5. Read the absolute high-speed counter's PV from IR 232 and IR 233 (port
1) or IR 234 and IR 235 (port 2) to determine the value before origin com-
pensation.
6. Turn ON the Absolute High-speed Counter 1 Origin Compensation Bit
(SR 25201) or Absolute High-speed Counter 2 Origin Compensation Bit
(SR 25202) from a Programming Device.
The compensation value will be written to DM 6611 (port 1) or DM 6612
(port 2) and the Origin Compensation Bit will be turned OFF automatically.
The compensation value will be stored as a 4-digit BCD between 0000 and
4095 regardless of whether the counter is set to BCD mode or 360 ° mode.
7. Read the high-speed counter's PV word to verify that origin compensation
has completed normally. (The PV should be 0000 after origin compensa-
tion.)
The compensation value will remain in effect until it is changed again by the
procedure above.
Use the following steps to program absolute high-speed counters 1 and 2.
Absolute high-speed counters 1 and 2 begin counting when the PC Setup set-
tings are enabled, but comparisons will not be made with the comparison
table and interrupts will not be generated unless the CTBL(63) instruction is
executed.
The PV of absolute high-speed counter 1 is maintained in IR 232 and IR 233,
and the PV of absolute high-speed counter 2 is maintained in IR 234 and IR
235.
15
Bit
DM 6634/DM 6635
00 to 12
00 to 11
Section 2-3
0
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