Omron CP1H-CPU - 05-2006 Operation Manual page 176

Overview of I/O Memory Area
Counter Area (C)
Condition Flags
Clock Pulses
Task Flag Area (TK)
Index Registers (IR)
Data Registers (DR)
Timer PVs
The PVs are read and written as words (16 bits). The PVs count up or down
as the timer operates.
There are two parts to the Counter Area: the Counter Completion Flags and
the Counter Present Values (PVs). Up to 4,096 counters with counter num-
bers C0 to C4095 can be used.
Counter Completion Flags
These flags are read as individual bits. A Completion Flag is turned ON by the
system when the corresponding counter counts out (i.e., when the set value is
reached).
Counter PVs
The PVs are read and written as words (16 bits). The PVs count up or down
as the counter operates.
These flags include the Arithmetic Flags, such as the Error Flag and Equals
Flag, which indicate the results of instruction execution as well as the Always
ON and Always OFF Flags. The Condition Flags are specified with symbols
rather than addresses.
The Clock Pulses are turned ON and OFF by the CPU Unit's internal timer.
These bits are specified with symbols rather than addresses.
A Task Flag will be ON when the corresponding cyclic task is in executable
(RUN) status and OFF when the cyclic task hasn't been executed (INI) or is in
standby (WAIT) status.
Index registers (IR0 to IR15) are used to store PLC memory addresses (i.e.,
absolute memory addresses in RAM) to indirectly address words in I/O mem-
ory. The Index Registers can be used separately in each task or they can be
shared by all tasks.
Data registers (DR0 to DR15) are used together with Index Registers. When a
Data Register is input just before an Index Register, the content of the Data
Register is added to the PLC memory address in the Index Register to offset
that address. The Data Registers can be used separately in each task or they
can be shared by all tasks.
Section 4-1
145