Memory Subsystem; Memory Subsystem Nomenclature - Intel SC5650HCBRP Product Specification

Functional Architecture
3.3

Memory Subsystem

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The Intel Xeon Processor 5500 Series and Intel
Server System SC5650HCBRP are populated on CPU sockets. Each processor installed on the
CPU socket has an integrated memory controller (IMC), which supports up to three DDR3
channels and groups DIMMs on the server boards into autonomous memory.
3.3.1

Memory Subsystem Nomenclature

The nomenclature for DIMM sockets implemented in the Intel
is represented in the following figures.
DIMMs are organized into physical slots on DDR3 memory channels that belong to
processor sockets.
The memory channels for CPU 1 socket are identified as Channels A, B, and C. The
memory channels for CPU 2 socket are identified as Channels D, E, and F.
The DIMM identifiers on the silkscreen on the board provide information about which
channel / CPU Socket they belong to. For example, DIMM_A1 is the first slot on
Channel A of CPU 1 socket. DIMM_D1 is the first slot on Channel D of CPU 2
Socket.
Processor sockets are self-contained and autonomous. However, all configurations
in the BIOS setup, such as RAS, Error Management, and so forth, are applied
commonly across sockets.
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The Intel Server System SC5650HCBRP supports six DDR3 memory channels (three channels
per processor) with two DIMM slots per channel, thus supporting up to twelve DIMMs in two-
processor configuration. See below figure for the Intel
slots arrangement.
30
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Xeon
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Intel order number E81443-002
Intel® Server System SC5650HCBRP TPS
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Processor 5600 Series on the Intel
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Server System SC5650HCBRP
Server System SC5650HCBRP DIMM
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Revision 1.2