Figure 27. Output Voltage Timing; Table 49. Output Voltage Timing; Table 50. Turn On / Off Timing - Intel SC5650HCBRP Product Specification

Power Sub-system
Item
T Output voltage rise time from each main output.
vout_rise
T All main outputs must be within regulation of each
vout_on
other within this time.
T All main outputs must leave regulation within this
vout_off
time.
* The 5VSB output voltage rise time shall be from 1.0 ms to 25.0 ms.
Vout
10%
Vout
V1
V2
V3
V4
Item
T Delay from AC being applied to 5VSB being within
sb_on_delay
regulation.
T Delay from AC being applied to all output voltages
ac_on_delay
being within regulation.
T Time all output voltages stay within regulation after
vout_holdup
loss of AC.
T Delay from loss of AC to de-assertion of PWOK
pwok_holdup
T Delay from PSON
pson_on_delay
regulation limits.
T Delay from PSON
pson_pwok
asserted.
T Delay from output voltages within regulation limits to
pwok_on
PWOK asserted at turn on.
86

Table 49. Output Voltage Timing

Description
T
vout rise
T
vout_on

Figure 27. Output Voltage Timing

Table 50. Turn On / Off Timing

Description
active to output voltages within
#
deactive to PWOK being de-
#
Intel order number E81443-002
Intel® Server System SC5650HCBRP TPS
Minimum Maximum
5.0* 70*
50
400
T
vout_off
Loading Minimum
75%
21
75% 20
5
100
Units
msec
msec
msec
Maximum Units
ms
1500
ms
2500
ms
ms
ms
400
ms
50
ms
500
Revision 1.2