Table 23. Voltage Regulation Limits; Table 24. Transient Load Requirements; Table 25. Capacitive Loading Conditions - Intel SC5650HCBRP Product Specification

Intel® Server System SC5650HCBRP TPS
4.1.3.6 Voltage Regulation
The power supply output voltages stay within the following voltage limits when operating at
steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise
specified in the Voltage Regulation Limits table. All outputs are measured with reference to the
GND. The +12V and +5VSB outputs are measured at the power distribution board output
harness connector.
Parameter
+ 12V
+ 5VSB
4.1.3.7 Dynamic Loading
The output voltages remain within limits specified for the step loading and capacitive loading
presented in the following table. The load transient repetition rate was tested between 5 Hz and
5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test
specification. The Δ step load may occur anywhere between the MIN load and MAX load
defined in the following table.
Output
12 V
+5 VSB
Note:
1. Step loads on each 12V output may happen simultaneously.
2. The +12V should be tested with 2200
4.1.3.8 Capacitive Loading
The power supply is stable and meets all requirements with the following capacitive loading
ranges. Minimum capacitive loading applies to static load only.
Revision 1.2

Table 23. Voltage Regulation Limits

Tolerance
- 5% / +5%
- 5% / +5%

Table 24. Transient Load Requirements

Max Δ Step Load Size
32.0 A 1
0.5 A

Table 25. Capacitive Loading Conditions

Output MIN
+12V 2000
+5VSB 1
Intel order number E81443-002
MIN NOM
+11.40 +12.00
+4.75 +5.00
Max Load Slew Rate
0.5 A/μs
0.5 A/μs
μ
F evenly split between the three +12V rails.
MAX
11,000
350
Power Sub-system
MAX Units
+12.60 Vrms
+5.25 Vrms
Test Capacitive Load
2200 μF
20 μF
Units
μF
μF
65