Intel SC5650HCBRP Product Specification page 91

Intel® Server System SC5650HCBRP TPS
System addressing 0/0/0
Address2/Address1/
Address0
PMBus device read B0h/B1h1
addresses 2
1
Non-redundant power supplies use the 0/0/0 address location
2
The addressing method uses the 7 MSB bits to set the address and the LSB to define whether
a device is reading or writing. The addresses defined above use 8 bits including the read/write
bit.
IPMI FRU Addressing:
If the power supply has a FRU (field replaceable unit) serial EEPROM; it should be located at
the following addresses.
System addressing 0/0/0
Address2/Address1/
Address0
FRU device addresses 2 A0h/A1h 1
1
Non-redundant power supplies use the 0/0/0 address location.
2
The addressing method uses the 7 MSB bits to set the address and the LSB to define whether
a device is reading or writing. The addresses defined above use 8 bits including the read/write
bit.
Revision 1.2
0/0/1 0/1/0 0/1/1
B2h/B3h B4h/B5h B6h/B7h
0/0/1 0/1/0 0/1/1
A2h/A3h A4hA5h A6h/A7h
Intel order number E81443-002
Power Sub-system
1/0/0 1/0/1 1/1/0
B8h/B9h BAh/BBh BCh/BDh
1/0/0 1/0/1 1/1/0
A8h/A9h AAh/ABh ACh/ADh
1/1/1
BEh/BFh
1/1/1
AEh/AFh
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