Table 26. Ripple And Noise; Table 27. Output Voltage Timing - Intel SC5650HCBRP Product Specification

Power Sub-system
4.1.3.9 Closed Loop Stability
The power supply is unconditionally stable under all line/load/transient load conditions, including
capacitive load ranges. A minimum 45-degree phase margin and -10dB-gain margin is met.
Closed-loop stability is ensured at the maximum and minimum loads, as applicable.
4.1.3.10 Common Mode Noise
The Common Mode Noise on any output does not exceed 350mV pk-pk over the frequency
band of 10 Hz to 20 MHz.
4.1.3.11 Ripple / Noise
The maximum ripple/noise output of the power supply is defined in the following table. This is
measured over a bandwidth of 0Hz to 20MHz at the power supply output connectors. A 10μF
tantalum capacitor in parallel with a 0.1μF ceramic capacitor is placed at the point of
measurement.
4.1.3.12 Forced Load Sharing
The +12V output has forced load sharing. The output shares within 10% at full load. All current
sharing functions are implemented internal to the power supply by making use of the 12LS
signal. The power distribution board connects the 12LS signal between the two power supplies.
The failure of a power supply does not affect the load sharing or output voltages of the other
supplies still operating. The supplies are able to load share with up to two power supplies in
parallel and can operate in a hot-swap / redundant 1+1 configuration. The 5Vsb output is not
required to actively share current between power supplies (passive sharing). The 5Vsb outputs
of the power supplies are connected together in the system so that a failure or hot swap of a
redundant power supply does not cause these outputs to go out of regulation in the system.
4.1.3.13 Timing Requirements
The timing requirements for power supply operation are as follows. The output voltages must
rise from 10% to within regulation limits (T
allowed to rise from 1.0 to 25 ms. All outputs rise monotonically. The following figure shows the
timing requirements for the power supply being turned on and off via the AC input, with PSON
held low and the PSON signal with the AC input applied.
Item Description
Tvout_rise Output voltage rise time from each main output.
66

Table 26. Ripple and Noise

+12V Output +5VSB Output
120mVp-p 50mVp-p
) within 5 to 70 ms except for 5VSB, which is
vout_rise

Table 27. Output Voltage Timing

Intel order number E81443-002
Intel® Server System SC5650HCBRP TPS
Minimum Maximum
5.0* 70*
Units
msec
Revision 1.2