Download Print this page

Juniper ACX5048 Manual page 33

Universal access router
Hide thumbs Also See for ACX5048:

Advertisement

Table 7: Protocols and Applications Supported by ACX Series Routers (continued)
Protocol or Application
Eight queues per port
Priority queuing
Rate control
Scheduling with two
different priorities
Low-latency queue (LLQ)
Weighted random early
detection (WRED) drop
profile (DP)
Classification—DSCP
Classification—MPLS EXP
Classification—IEEE 802.1p
Rewrite—DSCP
Rewrite MPLS EXP
Rewrite 802.1p
Rewrite MPLS and DSCP to
different values
Timing
Timing-1588-v2,
1588-2008–backup clock
Synchronous Ethernet
Building-integrated timing
supply (BITS)
Clock synchronization
Redundant clock (multiple
1588 masters)
Transparent clock
OAM, Troubleshooting, Manageability, Lawful Intercept
Copyright © 2015, Juniper Networks, Inc.
ACX1000
ACX1100
ACX2000
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
12.2
12.2R2
12.2
Chapter 1: System Overview and Architecture
ACX2100
ACX4000
ACX5048
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
15.1X54–D20
12.2R2
12.3x51-D10
12.2R2
12.3x51-D10
12.2R2
12.3x51-D10
12.2R2
12.3x51-D10
15.1X54-D20
ACX5096
15.1X54–D20
15.1X54–D20
15.1X54–D20
15.1X54–D20
15.1X54–D20
15.1X54–D20
15.1X54–D20
15.1X54–D20
15.1X54–D20
15.1X54–D20
15.1X54–D20
15.1X54–D20
15.1X54–D20
15.1X54-D20
13

Advertisement

loading

This manual is also suitable for:

Acx5096Acx5000Acx5048-acAcx5048-dcAcx5096-acAcx5096-dc