Omron Sysmac CS1 Operation Manual page 100

Customizable counter units
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AR Area
Address
Bits
Function
AR 09
00
High-speed
counter 1
commands
01
02
03
04
05 to
(Reserved
07
by
system.)
80
Details
High-speed
OFF: Stops counter operation. The
Counter
high-speed counter PV is held.
Start Bit
ON: Starts counter operation. The
high-speed counter PV is not reset.
High-speed
OFF: If the counter reset method is set to a
Counter
software reset in the Unit Setup Area
Reset Bit
(DM 6605 and DM 6607), the high-speed
counter PV is not cleared when internal I/O
refresh is performed in the Customizable
Counter Unit. If the counter reset method is
set to a phase Z + software reset, phase-Z
input is disabled.
ON: If the counter reset method is set to a
software reset in the Unit Setup Area
(DM 6605 and DM 6607), the high-speed
counter PV is cleared when internal I/O
refresh is performed in the Customizable
Counter Unit. If the counter reset method is
set to a phase Z + software reset, phase-Z
input is enabled.
Measure-
OFF: Measurement for high-speed counter
ment Start
rate of change or frequency measurement
Bit (mea-
is disabled.
surement
ON: Starts measurement for high-speed
mode 1 or 2)
counter rate of change or frequency
measurement.
Note 1: Frequency measurement is
possible only with counter 1.
Note 2: This bit is valid only when the
measurement mode set in the Unit Setup
Area (DM 6606 and DM 6608) is set to
high-speed counter rate of change
(measurement mode 1) or frequency
measurement (measurement mode 2).
Measure-
Specifies the direction (up or down) of the
ment Direc-
pulse input for which frequency
tion Specifi-
measurement is performed.
cation Bit
OFF: Up
(measure-
ON: Down
ment mode
Note: Be sure to set this bit before turning
2)
ON the Measurement Start Bit.
Range
OFF: The instruction execution result
Comparison
(AR 10) or the output bit pattern (AR 11)
Result Clear
that is output when the CTBL instruction is
Bit
executed for a range comparison on the
high-speed counter is not cleared.
ON: The instruction execution result
(AR 10) or the output bit pattern (AR 11)
that is output when the CTBL instruction is
executed for a range comparison on the
high-speed counter is cleared.
---
---
Section
6-4
Controlled
Forced
by
set/reset
User
Enabled

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