Reset Circuit - Citizen CL-E700 series Technical Manual

+3VIO and +5VIO:
+3VIO and +5VIO are the power supply for driving circuits. Since pin 2 (V3IOON) of the FPGA
is at "High" level and Q26/Q25 and Q24/Q22 turn ON, +3VIO and +5VIO are normally supplied
to the subsequent circuit.
However, in power saving mode, V3IOON goes to "Low" level, and Q26/Q25 and Q24/Q22
turn OFF. Thus, supply of +3VIO and +5VIO stops.

(2) Reset circuit

This circuit performs the system reset.
When power is turned ON, +3.3V gradually increases from 0V. When the voltage at pin 1 (VIN)
of the voltage detector (U2) reaches approx. at 2.8 V, pin 4 (nRST) of U2 changes from "Low"
level to "High" level.
While the nRST signal is "Low", the CPU (U1A) and the FPGA (U5) are reset.
The CPU outputs the nRSTGA signal to reset the FPGA and other circuits. Also the CPU
outputs the nRSTIF signal to reset the I/F circuits.
+3.3V
C26
[SA Main PCB]
+3.3V
0V
H
nRST
L
+3.3V
U2
Voltage Detector
1 4
VIN
OUT
3
2
Cd
VSS
XC6119N28ANR-G
Power ON
+3.3V
Reset
L : Reset
R16
nRST
nRSTGA
C27
C47
R30
C28
R11
R17
nRSTV3
2-39
Chapter 2 Operating Principles
2-2.
Operation of Control Parts
U1A
CPU
92
nRST
64
157
nRSTIF
(To I/F circuits)
nRSTGA
(To other circuits)
U5
FPGA
21_R1
R1
21_P1
P1
CL-E700 series