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Chapter 2:
Configuration Interfaces
For custom applications where a microprocessor or CPLD is used to configure a single
Virtex-4 device, either Master or Slave SelectMAP mode can be used
Xilinx
microprocessor). Refer to
RDWR_B, and BUSY signals.
Notes relevant to
1.
2.
3.
4.
5.
6.
7.
Multiple Device SelectMAP Configuration
Multiple Virtex-4 devices in Slave SelectMAP mode can be connected on a common
SelectMAP bus
RDWR_B, BUSY, PROGRAM_B, DONE, and INIT_B share a common connection between
all of the devices. To allow each device to be accessed individually, the CS_B (Chip Select)
inputs must not be tied together. External control of the CS_B signal is required and is
usually provided by a microprocessor or CPLD.
If Readback is going to be performed on the device after configuration, the RDWR_B and
BUSY signals must be handled appropriately. (For details, refer to
42
Application Note XAPP502
"SelectMAP Data Loading"
ADDRESS
DATA
CSO
CS1
WE
OE
Microprocessor
Figure 2-13: Single Slave Device SelectMAP Configuration
from Microprocessor and CPLD
Figure
2-13:
This schematic is from
Xilinx Application Note
implementations.
The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. In this arrangement, the active
DONE driver can be enabled, eliminating the need for an external pull-up resistor.
The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.
The BUSY signal can be left unconnected if readback is not needed.
The CS_B and RDWR_B signals can be tied to ground if only one FPGA is going to be
configured and readback is not needed.
The CCLK net requires Thevenin parallel termination. See
Configuration Clock (CCLK)," page
(Figure
2-14). In a SelectMAP bus, the data pins (SelectMAP data, CCLK,
www.xilinx.com
for information on configuring Virtex devices using a
for details on handling the CS_B,
Program
Register
Config.
CPLD
Register
Input
Register
Used for storage
Memory
of the configuration
bitstream
XAPP502. It is one of many possible
34.
Virtex-4 FPGA Configuration User Guide
(Figure
2-13). See
(7)
PROGRAM_B
CS_B
RDWR_B
CCLK
D[0:7]
Virtex-4
(7)
Slave
(2)
(3)
SelectMAP
INIT_B
DONE
BUSY
ug071_19_073007
"Board Layout for
Chapter
8)
UG071 (v1.12) June 2, 2017
R
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