Usb Controller With Host And Peripheral Ports; Xilinx Xcf32P Platform Flash Configuration Storage Device; Jtag Configuration Port - Xilinx M401 User Manual

Detailed Description

22. USB Controller with Host and Peripheral Ports

A Cypress CY7C67300 embedded USB host controller provides USB connectivity for the
board. The USB controller supports host and peripheral modes of operation. The USB
controller has two serial interface engines (SIE) that can be used independently. SIE1 is
connected to the USB Host 1 connector (J19) and the USB Peripheral 1 connector (J2). SIE2
is connected only to the USB Peripheral 2 connector.
Note:
peripheral connector, but not both at the same time.
The USB controller has an internal microprocessor to assist in processing USB commands.
The firmware for this processor can be stored in its own dedicated IIC EEPROM (U17) or
can be downloaded from a host computer via a peripheral connector. The USB controller's
serial port is connected to J27 through an RS-232 transceiver to assist with debug.

23. Xilinx XCF32P Platform Flash Configuration Storage Device

Xilinx XCF32P Platform Flash configuration storage device offers a convenient and
easy-to-use configuration solution for the FPGA. The Platform Flash memory holds up to
four separate configuration images (two images on the ML402 board) that can be accessed
through the configuration address switches. To use the Platform Flash memory to
configure the FPGA, the configuration selector switch (SW12) must be set to the Plat Flash
position.
The Platform Flash memory can program the FPGA by using the master or slave
configuration in serial or parallel (SelectMap) modes. The Platform Flash memory is
programmed using Xilinx iMPACT software through the board's JTAG chain. See the
"Configuration Options," page 31

24. JTAG Configuration Port

The JTAG configuration port for the board (J20) allows for device programming and FPGA
debug. The JTAG port supports the Xilinx Parallel Cable III or Parallel Cable IV products.
Third-party configuration products might also be available. The JTAG chain can also be
extended to an expansion board by setting jumper J26 accordingly. See the
Options," page 31
www.BDTIC.com/XILINX
28
When using SIE1, the port can only be configured at boot-up to use either the host or
section for more information.
www.xilinx.com
section for more information.
ML401/ML402/ML403 Evaluation Platform
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"Configuration
UG080 (v2.5) May 24, 2006