Configuration Register (Boundary-Scan); Usercode Register; User1, User2, User3, And User4 Registers; Using Boundary-Scan In Virtex-4 Devices - Xilinx Virtex-4 Configuration User Manual

Chapter 3: Boundary-Scan and JTAG Configuration
Table 3-5: Example JTAG IDCODE Concatenation (Continued)
Notes:
1. Does not reflect the actual device array size.

Configuration Register (Boundary-Scan)

The configuration register is a 64-bit register. This register allows access to the
configuration bus and readback operations.

USERCODE Register

The USERCODE instruction is supported in the Virtex-4 family. This register allows a user
to specify a design-specific identification code. The USERCODE can be programmed into
the device and can be read back for verification later. The USERCODE is embedded into
the bitstream during bitstream generation (BitGen -g UserID option) and is valid only
after configuration. If the device is blank or the USERCODE was not programmed, the
USERCODE register contains 0xFFFFFFFF.

USER1, USER2, USER3, and USER4 Registers

The USER1, USER2, USER3, and USER4 registers are only available after configuration.
These four registers must be defined by the user within the design. These registers can be
accessed after they are defined by the TAP pins.
The BSCAN_VIRTEX4 library macro is required when creating these registers. This symbol
is only required for driving internal scan chains (USER1, USER2, USER3, and USER4).
A common input pin (TDI) and shared output pins represent the state of the TAP controller
(RESET, SHIFT, and UPDATE). Unlike earlier FPGA families that required the BSCAN
macro to dedicate TAP pins for Boundary-Scan, Virtex-4 TAP pins are dedicated and do
not require the BSCAN_VIRTEX4 macro for normal Boundary-Scan instructions or
operations. For HDL, the BSCAN_VIRTEX4 macro must be instantiated in the design.

Using Boundary-Scan in Virtex-4 Devices

Characterization data for some of the most commonly requested timing parameters shown
in
Characteristics table.
66
vvvv
hex
<v>
(1)
XC4VFX40 bin
<vvvv>
hex
<v>
XC4VFX60 bin
<vvvv>
hex
<v>
XC4VFX100 bin
<vvvv>
hex
<v>
XC4VFX140 bin
<vvvv>
hex
<v>
Figure 3-5 are listed in the
www.xilinx.com
ffff fffa aaaa
1 E 6
0001 1110 1001
1 E 8
0001 1110 1011
1 E B
0001 1110 1110
1 E E
0001 1111 0001
1 F 1
Virtex-4 FPGA Data Sheet
Virtex-4 FPGA Configuration User Guide
aaaa cccc cccc
4 0 9
0100 0000 1001
C 0 9
0100 0000 1001
4 0 9
0100 0000 1001
4 0 9
0100 0000 1001
4 0 9
in the Configuration Switching
UG071 (v1.12) June 2, 2017
R
ccc1
3
0011
3
0011
3
0011
3
0011
3