Ganged Serial Configuration - Xilinx Virtex-4 Configuration User Manual

R
Maximum CCLK Rate Varies Between Xilinx Device Families
Older Xilinx device families require slower CCLK rates than Virtex-4 devices. For mixed
serial daisy chains, ensure the Master device does not toggle CCLK faster than the slowest
device can tolerate.
PROM File Considerations
The PROM file for a serial daisy chain is larger than the sum of all bitstreams due to
additional configuration instructions. See

Ganged Serial Configuration

More than one device can be configured simultaneously from the same bitstream using a
ganged serial configuration setup
configuration pins are tied together such that each device sees the same signal transitions.
One device is typically set for Master serial mode (to drive CCLK) while the others are set
for Slave serial mode. For ganged serial configuration, all devices must be identical.
Configuration can be driven from a configuration PROM or from an external configuration
controller.
Notes relevant to
1.
2.
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Xilinx
Serial PROM
DATA
CLK
CE
RESET/OE
PROGRAM
Figure 2-10: Ganged Serial Configuration
Figure 2-10:
For ganged serial configuration, the optional DONE driver must be disabled for all
devices if one device is set for Master mode, because each device might not start up on
exactly the same CCLK cycle. An external pull-up resistor is required in this case.
The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
www.xilinx.com
Serial Configuration Interface
"Generating PROM Files."
(Figure 2-10). In this arrangement, the serial
M0 M1
(8)
M2
DIN DOUT
CCLK
Virtex-4
Master
(8)
(1)
Serial
PROGRAM_B
DONE INIT_B
M0 M1
M2
DIN
DOUT
CCLK
Virtex-4
Slave
Serial
PROGRAM_B
DONE
INIT_B
ug071_15_073007
(2)
37