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Frame ECC Logic
Using Frame ECC Logic
Configurable memory is highly reliable, however to provide extra reliability, the solution
explained in this chapter has been provided.
The Frame error correction code (ECC) logic of the Virtex®-4 FPGA is designed to detect
single- or double-bit errors in configuration frame data. It uses SECDED (Hamming code)
parity values based on the frame data generated by BitGen. During readback, the Frame
ECC logic calculates a syndrome value using all the bits in the frame, including the ECC
bits. If the bits have not changed from the original programmed values, then the syndrome
are all 0s. If a single bit has changed, including any of the ECC bits, then the location of the
bit is indicated by syndrome bits 10:0 and syndrome bit 11 is 1. If two bits have changed,
then syndrome bit 11 is 0 and the remaining bits is non-zero and meaningless. If more than
two bits have changed then the syndrome is indeterminate. The error output of the block is
asserted if one or two bits have changed, indicating that action needs to be taken.
To use the Frame ECC logic, FRAME_ECC _VIRTEX4 must be instantiated in the user's
design, and readback must be performed through SelectMAP, JTAG, or ICAP. At the end of
each frame of readback, the syndrome_valid signal is asserted for one cycle of the readback
clock (CCLK, TCK, or ICAP_CLK). The number of cycles required to read back a frame
varies with the interface used. Refer to
Verification,"
The FRAME_ECC_VIRTEX4 logic does not repair changed bits; this requires a user design.
The design must be able to store at least one frame of data, or be able to fetch original
frames of data for reload. A single frame is 1,312 bits. Following is an example of a simple
repair implementation:
1.
2.
3.
4.
The syndrome bits S[10:0] are derived from the Hamming parity bits, while S[11] is derived
from the overall parity bit. The syndrome bit is interpreted as follows:
S[11]
S[11]
patch (indirectly).
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
for further information.
A frame is read out through ICAP and stored in block RAM. The frame address must
be generated as each frame is read.
If an error is indicated by the error output of the FRAME_ECC block, then the readback
is halted and the syndrome value saved. If bit 11 is 0, then the whole frame must be
restored. If bit 11 is 1, then bits 10:0 are used to locate the error bit in the saved frame,
and the bit inverted.
The repaired frame is then written back into the frame address generated in step 1.
Readback then begins again with the next frame address.
=
=
0: no error.
0, S[10:0]
=
≠
0: single bit (SED) error; S[10:0] denotes location of bit to
1, S[10:0]
www.xilinx.com
Chapter 8, "Readback and Configuration
Chapter 4
75
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