Configuring Through Boundary-Scan - Xilinx Virtex-4 Configuration User Manual

R
For further information on the startup sequence, bitstream, and internal configuration
registers referenced here, refer to

Configuring Through Boundary-Scan

One of the most common Boundary-Scan vendor-specific instructions is the configure
instruction. An individual Virtex-4 device can be configured through JTAG on power-up. If
the Virtex-4 device is configured on power-up, it is advisable to tie the mode pins to the
Boundary-Scan configuration mode settings: 101 (M2 = 1, M1 = 0, M0 = 1).
The configuration flow for Virtex-4 device configuration with JTAG is shown in
The sections that follow describe how the Virtex-4 device can be configured as a single
device through the Boundary-Scan or as part of a multiple-device scan chain.
A configured device can be reconfigured by toggling the TAP and entering a CFG_IN
instruction after pulsing the PROGRAM pin or issuing the shut-down sequence. (Refer to
Figure
Designers who wish to implement the Virtex-4 JTAG configuration algorithm are
encouraged to use the SVF-based flow provided in
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1
TMS
TDI
TCK
TDO
Data to be captured
Data to be driven out
Figure 3-5: Virtex-4 Boundary-Scan Port Timing Waveforms
3-6.)
www.xilinx.com
T
T
TCKTAP
TAPTCK
T
TCKTDO
Data Valid
Data Valid
"Setup (Steps 1-3)" in Chapter
Xilinx Application Note
ug071_35_121703
1.
Figure 3-6.
XAPP058.
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