Single Device Selectmap Configuration - Xilinx Virtex-4 Configuration User Manual

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Single Device SelectMAP Configuration

The simplest way to configure a single device in SelectMAP mode is to connect it directly
to a parallel configuration PROM as shown in
is set for Master SelectMAP mode, and the RDWR_B and CS_B pins are tied to Ground for
continuous data loading (see
Notes relevant to
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The CCLK net requires Thevenin parallel termination. See
11. The CCLK pin is an output and an input.
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Xilinx
Serial PROM
Figure 2-12: Single Device Master SelectMAP Configuration
Figure 2-12:
The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. In this arrangement, the active
DONE driver can be enabled, eliminating the need for an external pull-up resistor.
The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.
The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial
PROMs can be cascaded to increase the overall configuration storage capacity.
The .bit file must be reformatted into a PROM file before it can be stored on the serial
PROM. Refer to the "Generating PROM Files"
On XC17V00 devices, the reset polarity is programmable. RESET should be set for
active Low when using an XC17V00 device in this setup.
The Xilinx PROM must be set for parallel mode. Note that this mode is not available
for all devices.
When configuring a Virtex-4 device in SelectMAP mode from a Xilinx configuration
PROM, the RDWR_B and CS_B signals can be tied Low (see
Loading").
The BUSY signal does not need to be monitored for this setup and can be left
unconnected (see "SelectMAP Data
Configuration Clock (CCLK)," page
www.xilinx.com
SelectMAP Configuration Interface
Figure 2-12. In this arrangement, the device
"SelectMAP Data Loading").
SelectMAP
M0
M1
M2
(10)
DATA[0:7] D[0:7]
CCLK CCLK
CF
PROGRAM_B
(10)
(1) (2)
CE DONE
RESET/OE INIT_B
RDWR_B
CS_B
section.
Loading").
34.
Virtex-4
Master
ug071_22_073007
"SelectMAP Data
"Board Layout for
41