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Chapter 2:
Configuration Interfaces
For configuration, RDWR_B must be set for write control (RDWR_B = 0). For readback,
RDWR_B must be set for read control (RDWR_B = 1) while CS_B is deasserted. (For
details, refer to
Changing the value of RDWR_B while CS_B is asserted triggers an ABORT if the device
gets a rising CCLK edge (see
can be tied to ground.
The RDWR_B signal is ignored while CS_B is deasserted. Read/write control of the data
pins is asynchronous. The FPGA actively drives SelectMAP data without regard to CCLK
if RDWR_B is set for read control (RDWR_B = 1, Readback) while CS_B is asserted.
CCLK
All activity on the SelectMAP data bus is synchronous to CCLK. When RDWR_B is set for
write control (RDWR_B = 0, Configuration), the FPGA samples the SelectMAP data pins
on rising CCLK edges. When RDWR_B is set for read control (RDWR_B = 1, Readback),
the FPGA updates the SelectMAP data pins on rising CCLK edges.
In Slave SelectMAP mode, configuration can be paused by stopping CCLK (see
Continuous SelectMAP Data
BUSY
BUSY is an output from the FPGA indicating when the device is ready to drive readback
data. Unlike earlier Virtex devices, Virtex-4 FPGAs never drive the BUSY signal during
configuration, even at the maximum configuration frequency with an encrypted bitstream.
The Virtex-4 device only drives BUSY during readback. (For details, refer to
When CS_B is deasserted (CS_B = 1), the BUSY pin is placed in a high-Z state.
BUSY remains in a high-Z state until CS_B is asserted. If CS_B is asserted before power up
(that is, if the pin is tied to ground), BUSY initially is in a high-Z state, then driven Low
after POR finishes, usually a few milliseconds (T
before INIT_B goes High.
Unless readback is used, the BUSY pin can be left unconnected.
Continuous SelectMAP Data Loading
Continuous data loading is used in applications where the configuration controller can
provide an uninterrupted stream of configuration data. After power-up, the configuration
controller sets the RDWR_B signal for write control (RDWR_B = 0) and asserts the CS_B
signal (CS_B = 0), causing the device to drive BUSY Low (this transition is asynchronous).
RDWR_B must be driven Low before CS_B is asserted, otherwise an ABORT occurs (see
"SelectMAP
On the next rising CCLK edge, the device begins sampling the SelectMAP data pins.
Configuration begins after the synchronization word is clocked into the device.
After the configuration bitstream is loaded, the device enters the startup sequence. The
device asserts its DONE signal (DONE=1) in the phase of the startup sequence that is
specified by the bitstream (see
controller should continue sending CCLK pulses until after the startup sequence has
46
Chapter
8)
"SelectMAP
Loading").
♦
If BUSY = 0 during readback, the SelectMAP data pins are driving valid readback
data.
♦
If BUSY = 1 during readback, the SelectMAP data pins are not driving valid
readback data.
ABORT").
www.xilinx.com
ABORT"). If readback is not needed, RDWR_B
), after V
BUSY
"Startup (Step 8)" in Chapter
Virtex-4 FPGA Configuration User Guide
"Non-
Chapter
8)
reaches V
but
CCINT
POR
1). The configuration
UG071 (v1.12) June 2, 2017
R
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