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Boundary-Scan and JTAG Configuration
Introduction
Virtex®-4 devices support the new IEEE 1532 standard for In-System Configuration (ISC),
based on the IEEE 1149.1 standard. The IEEE 1149.1 Test Access Port and Boundary-Scan
Architecture is commonly referred to as JTAG. JTAG is an acronym for the Joint Test Action
Group, the technical subcommittee initially responsible for developing the standard. This
standard provides a means to ensure the integrity of individual components and the
interconnections between them at the board level. With multi-layer PC boards becoming
increasingly dense and more sophisticated surface mounting techniques in use, Boundary-
Scan testing is becoming widely used as an important debugging standard.
Devices containing Boundary-Scan logic can send data out on I/O pins in order to test
connections between devices at the board level. The circuitry can also be used to send
signals internally to test the device-specific behavior. These tests are commonly used to
detect opens and shorts at both the board and device level.
In addition to testing, Boundary-Scan offers the flexibility for a device to have its own set
of user-defined instructions. The added common vendor-specific instructions, such as
configure and verify, have increased the popularity of Boundary-Scan testing and
functionality.
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1
The Virtex-4 family is fully compliant with the IEEE Standard 1149.1 Test Access Port and
Boundary-Scan Architecture. The architecture includes all mandatory elements defined in
the IEEE 1149.1 Standard. These elements include the Test Access Port (TAP), the TAP
controller, the instruction register, the instruction decoder, the Boundary-Scan register, and
the bypass register. The Virtex-4 family also supports a 32-bit identification register and a
configuration register in full compliance with the standard. Outlined in the following
sections are the details of the JTAG architecture for Virtex-4 devices.
Test Access Port
The Virtex-4 TAP contains four mandatory dedicated pins as specified by the protocol
given in
pins and one output pin control the 1149.1 Boundary-Scan TAP controller. Optional control
pins, such as TRST (Test Reset) and enable pins might be found on devices from other
manufacturers. It is important to be aware of these optional signals when interfacing
Xilinx® devices with parts from different vendors, because they might need to be driven.
The TAP controller is a state machine (16-states) shown in
TAP pins are outlined below.
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Table 3-1
and illustrated in
www.xilinx.com
Figure
3-1, a typical JTAG architecture. Three input
Figure
Chapter 3
3-2. The four mandatory
57
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