Device Configuration - Xilinx ZC702 User Manual

Device Configuration

Zynq-7000 XC7Z020 SoC uses a multi-stage boot process that supports both a non-secure
and a secure boot. The PS is the master of the boot and configuration process. For a secure
boot, the PL must be powered on to enable the use of the security block located within the
PL, which provides 256-bit AES and SHA decryption/authentication.
The ZC702 board supports these configuration options:
• PS Configuration: Quad SPI flash memory
• PS Configuration: Processor System Boot from SD Card (J64)
• PL Configuration: USB JTAG configuration port (Digilent module)
• PL Configuration: Platform cable header J2 and flying lead header J58 JTAG
configuration ports
Designs using serial configuration based on Quad-SPI flash memory can take advantage of
TIP:
low-cost commodity SPI flash memory.
The JTAG configuration option is selected by setting SW16 as shown in
as described in
details. SW10 is callout
Table 1-2: Switch SW16 Configuration Option Settings
Boot Mode
(1)
JTAG mode
Independent JTAG mode
Quad SPI mode
SD mode
MIO configuration pin
Notes:
1. Default switch setting
For more information about Zynq-7000 SoC configuration settings, see the Zynq-7000 SoC
Note:
Technical Reference Manual (UG585)
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Programmable Logic JTAG Programming Options
23 in Figure 1-2.
SW16.1
0
1
0
0
MIO2
[Ref
www.xilinx.com
SW16.2 SW16.3
0 0
0 0
0 0
0 1
MIO3 MIO4
2].
Feature Descriptions
Table 1-2 and SW10
for PL configuration
SW16.4 SW16.5
0 0
0 0
1 0
1 0
MIO5 MIO6
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