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Chapter 2:
Configuration Interfaces
Ganged SelectMAP
It is also possible to configure simultaneously multiple devices with the same
configuration bitstream by using ganged SelectMAP configuration. In a ganged
SelectMAP arrangement, the CS_B pins of two or more devices are connected together (or
tied to ground), causing all devices to recognize data presented on the SelectMAP data
pins.
All devices can be set for Slave SelectMAP mode if an external oscillator is available, or one
device can be designated as the Master device, as illustrated in
Notes relevant to
1.
2.
3.
4.
5.
44
Xilinx
Serial PROM
DATA[0:7]
CCLK
CF
CE
RESET/OE
Figure 2-15: Ganged SelectMAP Configuration
Figure
2-15:
The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. In this arrangement, the active
DONE driver must be disabled for both devices.
The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.
The BUSY signal is not used for ganged SelectMAP configuration.
The PROM in this diagram represents one or more Xilinx Platform Flash PROMs.
Multiple serial PROMs can be cascaded to increase the overall configurations storage
capacity.
www.xilinx.com
M1
M0
M2
Virtex-4
SelectMAP
D[0:7]
CCLK
PROGRAM_B
INIT_B
RDWR_B
CS_B
M1
M0
M2
Virtex-4
(10)
SelectMAP
D[0:7]
CCLK
PROGRAM_B
(2)
INIT_B
(10)
RDWR_B
CS_B
Virtex-4 FPGA Configuration User Guide
Figure
2-15.
Master
BUSY
(1)
DONE
Slave
BUSY
DONE
ug071_24_073007
UG071 (v1.12) June 2, 2017
R
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