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Reconfiguration Techniques
Dynamic Reconfiguration of Functional Blocks (DRP)
Background
In the Virtex® family of FPGAs, the Configuration Memory is used primarily to implement
user logic, connectivity and I/Os, but it is also used for other purposes. For example, it is
used to specify a variety of static conditions in functional blocks, such as Digital Clock
Managers (DCMs) and RocketIO™ Multi-Gigabit Transceivers (MGTs).
Sometimes an application requires a change in these conditions in the functional blocks
while the block is operational. This can be accomplished through the global Internal
Configuration Access Port (ICAP), or through partial dynamic reconfiguration using JTAG
or SelectMAP in the Persist mode. However, the reconfiguration port that is an integral
part of each functional block simplifies this process greatly. Such configuration ports exist
in the DCMs and RocketIO MGTs.
Overview
This document describes the addressable, parallel write/read configuration memory that
is implemented in each functional block that might require reconfiguration. This memory
has the following attributes:
•
•
•
The address space can include status (read-only) and function enables (write-only). Note
that read-only and write-only operations can share the same address space.
shows how the configuration bits drive the logic in functional blocks directly in earlier
FPGA families, and
read or write the configuration bits.
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
It is directly accessible from the FPGA fabric. Configuration bits can be written to
and/or read from depending on their function.
Each bit of memory is initialized with the value of the corresponding configuration
memory bit in the bitstream. Memory bits can also be changed later through the ICAP.
The output of each memory bit drives the functional block logic, so the content of this
memory determines the configuration of the functional block.
Figure 6-2
All configuration bits
for this block
Configuration Logic
Figure 6-1: Block Configuration Logic without Dynamic Interface
www.xilinx.com
shows how the reconfiguration logic changes the flow to
to block logic
Functional Block (DCM or MGT)
Chapter 6
Figure 6-1
ds071_46_071505
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