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Chapter 2:
Configuration Interfaces
Notes relevant to
1.
2.
3.
4.
5.
6.
7.
8.
9.
Slave Serial Configuration
Slave serial configuration is typically used for devices in a serial daisy chain, or when
configuring a single device from an external microprocessor or CPLD. Design
considerations are similar to Master serial configuration except for the direction of CCLK.
A single device in Slave serial mode cannot simply be connected to a PROM, because
CCLK is an input on both devices.
Serial Daisy Chains
Multiple Virtex-4 devices can be configured from a single configuration source by
arranging the devices in a serial daisy chain. In a serial daisy chain, devices receive their
configuration data through their DIN pin, passing configuration data along to
downstream devices through their DOUT pin. The device closest to the configuration data
source is considered the most upstream device, while the device furthest from the
configuration data source is considered the most downstream device.
In a serial daisy chain, the configuration clock is typically provided by the most upstream
device in Master serial mode. All other devices are set for Slave serial mode.
illustrates this configuration.
Alternatively, if a CPLD or microprocessor is used as a configuration controller, all devices
can be set for Slave serial mode. (See
Microprocessor or CPLD," page
30
Figure
2-3:
The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. The DONE pin has a programmable
active driver. To enable it, enable the DriveDONE option in BitGen.
The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
The BitGen startup clock setting must be set for CCLK for serial configuration. The
oscillator frequency can be selected in BitGen (default is 4 MHz). Selectable
frequencies are 4, 5, 7, 8, 9, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, and 60 MHz. Because
the oscillator can vary by ± 50%, select a maximum frequency not to exceed the F
of the configuration device.
The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial
PROMs can be cascaded to increase the overall configuration storage capacity.
The .bit file must be reformatted into a PROM file before it can be stored on the serial
PROM. Refer to the
"Generating PROM Files"
On XC17V00 PROMs, the reset polarity is programmable. RESET should be set for
active Low when using an XC17V00 device in this setup.
Connect pull-up resistors to V
The CCLK net requires Thevenin parallel termination. See
Configuration Clock (CCLK)," page
The CCLK pin is an output and an input.
www.xilinx.com
section.
(identical to V
CC_CONFIG
34.
"Configuring a Serial Daisy Chain with a
32.)
Virtex-4 FPGA Configuration User Guide
Bank 0).
CC
"Board Layout for
Figure 2-4
UG071 (v1.12) June 2, 2017
R
MAX
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