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R
as a percentage of the clock. Just as in legacy mode, PSDONE indicates completion of the
phase shift. If DLL_PHASE_SHIFT_LOCK_BY1 = 0, then the lower three bits of phase shift
value are ignored, because it works on eight tabs as a unit.
Phase shift overflow does not toggle in the Direct Mode if the end of the delay line is
reached.
It is recommended that the same clock be used for DCLK and PSCLK. Although the
PSDONE pin is a function of the PSCLK domain, the data written to the DRP is in the
DCLK domain. If this cannot be done, then the following two scenarios should be
considered:
1.
2.
Setting a direct phase shift value:
1.
2.
3.
4.
ICAP - Internal Configuration Access Port
The Internal Configuration Access Port (ICAP) allows access to configuration data in the
same manner as SelectMAP. ICAP has the same interface signaling as SelectMAP other
than the data bus, which is separated into read and write data buses. ICAP has a chip-
select signal (CS), a read-write control signal (RD), a clock (CLK), a write data bus (DIN),
and a read data bus (OUT). ICAP can be configured to two different data bus widths, 8 bits
or 32 bits. When the 8-bit ICAP interface is used, the data is byte-reversed like SelectMAP.
When the 32-bit interface is used, the data is not reversed, which is the same as
SelectMAP32.
The ICAP interface can be used to perform readback operations or partial reconfiguration.
When using ICAP for partial reconfiguration, the user must avoid changing the logic or
interconnect which the ICAP is itself connected to. ICAP can also be used to read or write
to the configuration registers, such as the STAT, CTL, or FAR registers. See
Configuration Registers through the SelectMAP Interface"
There are two ICAP sites in Virtex-4 devices: TOP and BOTTOM. The implementation has
the two interfaces share the same underlying logic. The only difference between them is
their location on the chip and the interconnect to which they can be connected. The two
interfaces can never be active at the same time. The default site for a single ICAP is the TOP
site, because the TOP site is active after configuration by default. If both sites are used, the
TOP site must be activated first before switching to the BOTTOM site. The process of
switching between the two sites is as follows:
1.
2.
3.
4.
5.
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Connect DCLK, but not PSCLK. PSDONE is not asserted. The phase shift value is
executed, although there is no indication when it is completed.
Connect PSCLK and DCLK to different sources. PSDONE is in the PSCLK domain
and can be asynchronous to DCLK.
If the CLKOUT_PHASE_SHIFT was not set to DIRECT, then write 00Dh (DI) to
DADDR address 56h. (DRP should not be used to change configuration memory other
than phase shift value.)
Write the desired tab value 0-3FFh (DI) (0-1023 tabs) to DADDR 55h.
Write to DADDR 11h to start the phase shift. (Data on DI does not matter.)
PSDONE asserts for one PSCLK cycle to indicate that the phase shift is done.
Synchronize the current interface (if it's not already synched).
Write bit 30 of the MASK register with a 1.
Write bit 30 of the CTL register with a 1 if switching to the BOTTOM site or a 0 if
switching to the TOP site.
Write the DESYNCH command to the CMD register.
Synchronize the new ICAP site.
www.xilinx.com
Dynamic Reconfiguration of Functional Blocks (DRP)
"Accessing
for details.
85
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