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X-Ref Target - Figure 1-26
Table 1-25
Table 1-25: XADC Header J19 Pinout
Net Name
VN, VP
XADC_VAUX0P, N
XADC_VAUX8N, P
DXP, DXN
XADC_AGND
XADC_VREF
XADC_VCC5V0
XADC_VCC_HEADER
VADJ
GND
XADC_GPIO_3, 2, 1, 0
Configuration Options
The FPGA on the VC709 board can be configured by the following methods:
•
•
See 7 Series FPGAs Configuration User Guide (UG470) for further details on configuration
modes.
The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0)
settings selected through DIP switch SW11.
settings.
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
XADC_VN
XADC_VAUX0P
XADC_VCC5V0
XADC_VAUX8N
XADC_DXP
VADJ
XADC_VREF
XADC_GPIO_1
XADC_GPIO_3
describes the XADC header J19 pin functions.
J19 Pin
Number
1, 2
Dedicated analog input channel for the XADC.
Auxiliary analog input channel 0. Also supports use as I/O inputs when
3, 6
anti-alias capacitor is not present.
Auxiliary analog input channel 8. Also supports use as I/O inputs when
7, 8
anti-alias capacitor is not present.
9, 12
Access to thermal diode.
4, 5, 10
Analog ground reference.
11
1.25V reference from the board.
13
Filtered 5V supply from board.
14
Analog 1.8V supply for XADC.
15
V
supply for bank which is the source of DIO pins.
CCO
16
Digital ground (board) reference
Digital I/O. These pins should come from bank 15. These I/Os should not be
19, 20, 17, 18
shared with other functions because they are required to support 3-state
operation.
Master BPI (uses the linear BPI flash).
JTAG (Digilent USB-to-JTAG Bridge only). See
information.
www.xilinx.com
J19
1
3
5
7
9
11
13
15
17
19
XADC_AGND
Figure 1-26: XADC header (J19)
Description
USB JTAG, page 23
Table 1-26
Configuration Options
2
XADC_VP
4
6
XADC_VAUX0N
XADC_VAUX8P
8
10
12
XADC_DXN
XADC_VCC_HEADER
14
16
18
XADC_GPIO_0
XADC_GPIO_2
20
GND
XADC_AGND
UG887_c1_26_090612
for more
lists the supported mode switch
61
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