Mpsoc Device Configuration - Xilinx ZCU102 User Manual

MPSoC Device Configuration

Zynq UltraScale+ XCZU9EG MPSoC devices use a multi-stage boot process documented in
the Boot and Configuration chapter of the Zynq UltraScale+ MPSoC Technical Reference
Manual (UG1085)
Switch SW6 configuration option settings are identified in
Table 2-4: Switch SW6 Configuration Option Settings
Boot Mode
JTAG
QSPI32
SD
Notes:
1. Default switch setting.
JTAG
Vivado, SDK, or third-party tools can establish a JTAG connection to the Zynq UltraScale+
MPSoC device through one of the three provided JTAG interfaces:
1. Xilinx platform USB or cable PC4 connector (J8)
2. ARM 20-pin JTAG connector (J6)
3. Digilent SMT2.5 USB-to-JTAG module with off-module micro-USB connector (J2)
Quad-SPI
Booting from the dual Quad-SPI nonvolatile configuration memory is accomplished by
storing a valid Zynq UltraScale+ MPSoC boot image into the Quad-SPI flash devices
connected to the MIO Quad-SPI interface, setting the boot mode pins SW6 [4:1] = QSPI32
(see Table 2-4), then either power-cycling or pressing the power-on reset (POR) pushbutton.
SW6 is callout 23 in
SD
Booting from an SD card is accomplished by storing a valid Zynq UltraScale+ MPSoC boot
image file onto an SD card (plugged into SD socket J100) connected to the MIO SD
interface, setting the boot mode pins SW6 [4:1] = SD (see
power-cycling or pressing the power-on reset (POR) pushbutton.
See the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085)
information about Zynq UltraScale+ MPSoC configuration options.
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
[Ref 2].
Mode Pins [3:0] Mode SW6 [4:1]
0000
(1)
0010
1110
Figure 2-1.
www.xilinx.com
Chapter 2: Board Setup and Configuration
Table
on, on, on, on
on, on, off, on
off, off, off, on
Table
2-4.
2-4), then either
[Ref 2] for more
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