Clocking Startup And Shutdown Sequences (Jtag) - Xilinx Virtex-4 Configuration User Manual

Chapter 3: Boundary-Scan and JTAG Configuration
to the ISC_Accessed state from the Operational state, the shutdown sequence is executed.
The I/Os are all either 3-stated or pulled up.
The startup sequence is executed when in the ISC_Accessed state. At the end of the startup
sequence, ISC_Enabled is cleared and the device moves to ISC_Complete. The minimum
clock cycle requirement is the number of clock cycles required to complete the startup
sequence. At the completion of the minimum required clock cycles, ISC_Enabled is
deasserted.
Whether the startup sequence is successful or not is determined by CRC or configuration
error status from the configuration processor. If the startup is completed, ISC_Done is
asserted; otherwise, ISC_Done stays Low. The I/Os are either 3-stated or pulled up.
When ISC_Done is set in ISC_Complete state, the device moves to the Operational state.
Otherwise, if ISC_Done is clear, the device moves to the Unprogrammed state. However, if
the TAP controller goes to the TLR state while the device is in ISC_Accessed state, and if
ISC_Done is set, then the device moves to the Operational state.
Though Operational, the I/O is not active yet because the startup sequence has not been
performed. The startup sequence has to be performed in the Operational state to bring the
I/O active.

Clocking Startup and Shutdown Sequences (JTAG)

There are three clock sources for startup and shutdown sequence: CCLK, UserCLK, and
JTAGCLK. Clock selection is set by BitGen. The startup sequence is executed in the
ISC_Accessed state. When it is clocked by JTAGCLK, the startup sequence receives the
JTAGCLK in TAP Run/Test Idle state while ISC_DISABLE is the current JTAG instruction.
The number of clock cycles in Run/Test Idle state for successful completion of
ISC_DISABLE is determined by the number of clock cycles needed to complete the startup
sequence.
When UserCLK or CCLK is used to clock the startup sequence, the user should know how
many JTAGCLK cycles should be spent in Run/Test Idle to complete the startup sequence
successfully.
The shutdown sequence is executed when the device transitions from the Operational to
the ISC_Accessed state. Shutdown is done while executing the ISC_ENABLE instruction.
When the shutdown sequence is clocked using JTAGCLK, the clock is supplied in the
Run/Test Idle state of the ISC_ENABLE instruction. The number of clock cycles in
Run/Test Idle is determined by the number of clock cycles needed to complete the
shutdown sequence.
When the shutdown sequence is clocked by CCLK or UserCLK, the user is responsible for
knowing how many JTAGCLK cycles in Run/Test Idle are needed to complete the
shutdown sequence.
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Note:
When configuring the device through JTAG, the startup and shutdown clock should
come from TCK, regardless of the selection in BitGen. In IEEE 1532 configuration
mode, the startup and shutdown clock source is always TCK.
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UG071 (v1.12) June 2, 2017
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