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User Access Register
Using the User Access Register
The User Access Register (USR_ACCESS_VIRTEX4) is a 32-bit register that allows data
from the bitstream to be directly accessible by the FPGA fabric. The register has two
outputs: the 32-bit DATA bus and a data_valid signal that is asserted for one cycle of the
configuration-data source clock whenever a new value is available. The configuration-data
source clock can be CCLK or TCK.
The UAR allows data from a bitstream data storage source (e.g., PROM) to be accessed by
the fabric after the FPGA has been configured. To accomplish this, the STARTUP_VIRTEX4
block should also be instantiated.
The STARTUP_VIRTEX4 block has inputs that allow the user to take control of the CCLK
and DONE pins after the EOS (End-Of-Startup) signal has been asserted. These pins are
USR_CCLK_O, USR_CCLK_TS, USR_DONE_O, and USR_DONE_TS. The BitGen option
-g DONE_cycle:KEEP should be used to prevent the DONE pin from going High,
because that can reset or disable the configuration storage source. The USR_CCLK_O pin
should be connected to a controlled clock in the fabric. The configuration device should
contain data with the USR_ACCESS register as the target. After EOS has been asserted, the
data can be loaded by clocking the USR_CCLK_O pin while keeping USR_CCLK_TS Low
(it can be tied Low in this usage).
The DATAVALID output indicates that a word is available on the data output port.
DATAVALID goes High for one CCLK cycle after the register is updated. A write to the
User Bitstream Access Register (AXSS) after configuration is required. Similar to other
configuration registers, the AXSS register can be accessed through the configuration
interface (e.g., JTAG, SelectMap, ICAP).
The USR_ACCESS register can be used to provide a single 32-bit constant value to the
fabric as an alternative to using a block RAM or LUTRAM to hold the constant.
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
www.xilinx.com
Chapter 5
77
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