Fpga Fabric Port Definition - Xilinx Virtex-4 Configuration User Manual

Chapter 6: Reconfiguration Techniques
Figure 6-3
Functional Block is expanded to show the actual signal names and directions.

FPGA Fabric Port Definition

Table 6-1, page
blocks can implement all or only a subset of these signals. The DCM chapter in the
Virtex-4 FPGA User Guide
shows the signals and functions implemented for the specific blocks. In general, the port is
a synchronous parallel memory port, with separate read and write buses similar to the
block RAM interface. Bus bits are numbered least-significant to most-significant, starting
at 0. All signals are active High.
80
Standard
Reconfiguration
Port (to fabric)
Logic Plane
All configuration bits
for this block
Configuration Logic Functional Block (DCM or MGT)
Figure 6-2: Block Configuration Logic with Dynamic Interface
is the same as Figure
DCLK
DEN
DWE
Standard
DADDR[m:0]
Reconfiguration
DI[n:0]
Port (to fabric)
DO[n:0]
DRDY
Logic Plane
All configuration bits
for this block
Configuration Logic Functional Block (DCM or MGT)
Figure 6-3: Block Configuration Logic Expanded to Show Signal Names
82, lists each signal on the FPGA Fabric port. The individual functional
and the
www.xilinx.com
CONTROLLER
Reconfigurable Bits
Non-reconfigurable Bits
6-2, except the port between the Logic Plane and
CONTROLLER
Reconfigurable Bits
Non-reconfigurable Bits
Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide
Virtex-4 FPGA Configuration User Guide
Block Status
(Read-Only Ports)
Function Enables
(Write-Only Ports)
to block logic
to block logic
ds071_42_071705
Block Status
(Read-Only Ports)
Function Enables
(Write-Only Ports)
to block logic
to block logic
ds071_43_071705
UG071 (v1.12) June 2, 2017
R