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Chapter 8:
Readback and Configuration Verification
Table 8-4: Status Register Readback Command Sequence (JTAG) (Continued)
The packets shifted in to the JTAG CFG_IN register are identical to the packets shifted in
through the SelectMAP interface when reading the STAT register through SelectMAP.
Configuration Memory Read Procedure (1149.1 JTAG)
The process for reading configuration memory from the FDRO register through the JTAG
interface is similar to the process for reading from other registers. However, additional
steps are needed to accommodate frame logic. Configuration data coming from the FDRO
register pass through the frame buffer, therefore the first frame of readback data is dummy
data and should be discarded (refer to the FDRI and FDRO register description). The 1149.1
JTAG readback flow is recommended for most users.
1.
2.
3.
4.
5.
6.
7.
106
Step
Description
Shift the contents of the STAT register out of the
CFG_OUT data register.
Shift the last bit of the STAT register out of the
CFG_OUT data register while exiting
5
SHIFT-DR.
Move into the Select-IR state.
Move into the Shift-IR State.
6
Reset the TAP Controller.
Reset the TAP controller.
Shift the CFG_IN instruction into the JTAG Instruction Register. The LSB of the
CFG_IN instruction is shifted first; the MSB is shifted while moving the TAP controller
out of the SHIFT-IR state.
Shift packet write commands into the CFG_IN register through the Shift-DR state:
a.
Write a dummy word to the device.
b. Write the Synchronization word to the device.
c.
Write a NOOP instruction to the device.
d. Write the RCRC command to the device.
e.
Write two dummy words to flush the packet buffer.
Shift the JSHUTDOWN instruction into the JTAG Instruction Register.
Move into the RTI state; remain there for 12 TCK cycles to complete the Shutdown
sequence. The DONE pin goes Low during the Shutdown sequence.
Shift the CFG_IN instruction into the JTAG Instruction Register.
Move to the Shift-DR state and shift packet write commands into the CFG_IN register:
a.
Write a dummy word to the device.
b. Write the Synchronization word to the device.
c.
Write a NOOP instruction to the device.
d. Write the write CMD register header.
e.
Write the RCFG command to the device.
f.
Write the write FAR register header.
g. Write the starting frame address to the FAR register (typically 0x0000000).
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Set and Hold
TDI
TMS
0
0xSSSSSSSS
S
1
X
1
X
0
X
1
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
R
# of
Clocks
(TCK)
31
1
3
2
5
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