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2-3-3
Main PWB
SBFM
SCAN
DIGKEY
OPWB
CIS
Image data
Basis signal
(CLK, MRE, HSYNC)
CIS
SHD
VSYNC
PWB
SPWB
Image data
Basis signal
(CLK, MRE, HSYNC)
SHD
PWB
VSYNC
CCD
PWB
LSU
PD
PWB
APC
PWB
PM
2-3-8
XIO
LCD
controller
CODE
DIMM
VXINSEL
H/L
Beam
BD+
detection
BD-
signal (BD)
RS422
Video LVDS signal
(3 beams)
Auto laser power control
signal (a, b, c)
Laser ON enable signal
(LDEN0)
D/A converter control signal for laser power adjust (DATA, CLK, LOAD)
24V, PLGREM, PLGCLK
PLGRDY
Figure 2-3-5 Main PWB block diagram
MPWB
Address bus/Data bus
EEPROM
Flash
RTC
ROM
Flash
Buffer
ROM
RE, WE, CS, RESET
CPUCLK
33 MHz
Image data
Basis signal(CLK, MRE, VSYNC)
Image data
Pseudo BD signal
Clock(ADCLK)
Horizontal scanning
synchronizing signal
(CCDSH)
Image data
Pseudo BD signal
Clock(ADCLK)
Horizontal scanning
synchronizing signal
(CCDSH)
Image data
Basis signal
(RVSTIN_b, RCKIN, MREVD)
Horizontal scanning synchronizing
signal (PHSYNC)
Vertical scanning synchronizing
signal (PVOUT)
OUTPEN
Cover open detection signal (R5V)
PVSYNC
Initial Laser ON signal (LDON)
Service Manual
SDRAM
SDRAM
CPU
*
Image
data
MIP
8 bit
for
Basis
CIS
signal
(WCK,
WVST,
*
MREID)
Image
data
8 bit
MIP
Basis
for
signal
CCD
(WCK,
WVST,
MREID)
CODEC
CODEC
Optional
printer
board
HDD
DIMM
EPWB
Y104350-7
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