Applications; Description - Texas Instruments TMS320C6745 Manual

TMS320C6745, TMS320C6747
SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014
– PRUSS can be Disabled via Software to
Save Power
– Standard Power-Management Mechanism
– Clock Gating
– Entire Subsystem Under a Single PSC Clock
Gating Domain
– Dedicated Interrupt Controller
– Dedicated Switched Central Resource
• USB 1.1 OHCI (Host) with Integrated PHY (USB1)
(TMS320C6747 Only)
• USB 2.0 OTG Port with Integrated PHY (USB0)
– USB 2.0 High- and Full-Speed Client
(TMS320C6747)
– USB 2.0 Full-Speed Client (TMS320C6745)
– USB 2.0 High-, Full-, and Low-Speed Host
(TMS320C6747)
– USB 2.0 Full- and Low-Speed Host
(TMS320C6745)
– High-Speed Functionality Available on
TMS320C6747 Device Only
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) RX and TX
• Three Multichannel Audio Serial Ports (McASPs):
– TMS320C6747 Supports 3 McASPs
– TMS320C6745 Supports 2 McASPs
– Six Clock Zones and 28 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable (McASP2)
– FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
1.2

Applications

• A/V Receivers
• Automotive Amplifiers
• Soundbars
1.3

Description

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP
core. It consumes significantly lower power than other members of the TMS320C6000™ platform of
DSPs.
The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design
manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .
The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program
cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-
associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared
between program and data space. L2 memory can be configured as mapped memory, cache, or
combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional
128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting
DSP performance.
2 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal
Processor
• Real-Time Clock with 32-kHz Oscillator and
• One 64-Bit General-Purpose Timer (Configurable
• One 64-Bit General-Purpose Watchdog Timer
• Three Enhanced Pulse Width Modulators
• Three 32-Bit Enhanced Capture (eCAP) Modules:
• Two 32-Bit Enhanced Quadrature Encoder Pulse
• TMS320C6747 Device:
• TMS320C6745 Device:
• Commercial, Industrial, Extended, or Automotive
•
•
•
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Product Folder Links: TMS320C6745 TMS320C6747
– RMII Media-Independent Interface
– Management Data I/O (MDIO) Module
Separate Power Rail (TMS320C6747 Only)
as Two 32-Bit Timers)
(Configurable as Two 32-Bit General-Purpose
Timers)
(eHRPWMs):
– Dedicated 16-Bit Time-Base Counter with
Period and Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric, or 3
Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
– Configurable as 3 Capture Inputs or 3 Auxiliary
Pulse Width Modulator (APWM) Outputs
– Single-Shot Capture of up to Four Event Time-
Stamps
(eQEP) Modules
– 256-Ball Pb-Free Plastic Ball Grid Array (PBGA)
[ZKB Suffix], 1.0-mm Ball Pitch
– 176-pin PowerPAD™ Plastic Quad Flat Pack
[PTP suffix], 0.5-mm Pin Pitch
Temperature
Home Theatre Systems
Professional Audio
Network Streaming Audio
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