Intel 2920 Design Handbook page 93

Analog signal processor
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APPLICATION EXAMPLES
+
~
SIGIN
---v.----
t
Go
Figure 7-8. Block Diagram of Complex 3 Pole 2 Zero Elliptical Digital Filter
ISIS-II 2920 ASSEMBLER XI02
ASSEMBLER INVOKED BY
AS2920 F IL TER
Three Pole Two Zero ElliptIcal Low-pass F)lter
LINE
LOC OBJECT SOURCE STATEMENT
I
.TITLE ('Three Pole Two ZeTo Elilptlcal Lou,-Pas5 Filter')
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SYMBOL
YI2
YOI
SIGOUT
Y~O
YII
YIO
YI2
EGU
YOI
SIGOUT
EGU
YI2
• POLE I
o
4008EF LOA YO I. YOO
I
40223E LOA
y~o.
DAR. R2
2 4000lC ADD YOO. YOI. RI
3 40007C ADD YOO. YOI. R4
4 40009C ADD YOO. YO I. R 5
5 40003B SUB YOO. YOI. RIO
• POLE 2 "
3
6 4200EF LOA Y12. YII
7 4608EF LOA YII. YIO
8 44085E LOA Y1 O. YOO. R3
9 4600BC ADD YIO.Yl1.R6
10 4600FD ADD YIO.YII.RO
I I 46003C ADD YIO.Yl1.R2
12 4400lA SUB YIO. Y12. RI
13 44005A SUB YIO. Y12. R3
14 44009A SUB YIO.Y12.R5
15 4400BA SUB YIO. Y12. R6
• ZERO I
"
2
16 4208ED ADD SIGOUT. YIO
17 42002A SUB SIGOUT.YII.R2
18 42008A SUB SIGOUT. YII. R5
19 4200EA SUB SIGOUT. YII. R8
20 4044CF LOA DAR. SIGOUT. Ll
END
VALUE
ASSEMBLY COMPLETE
YOI=YOO
YOO=GO*XO (INPUT SCALED DOWN BY 4)
YOO= GO*XO + BOI*YOI
YI2 = YII
YII = YIO
YIO = G1*YOO (STAGE PROPAGATION SCALED DOWN BY 8)
YIO = BII*YII
YIO = BII*YII
+
B22*Y12 + GI*YOO
SIGOUT
=
AIO*YI0 + A12»Y12
SIGOUT
=
AI0*YI0
+
All*Yll
+
A12*Y12
OUTPUT SCALED UP BY 2
Figure 7-9. Complex Digital Filter Program
7-6

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