Intel 2920 Design Handbook page 76

ADVANCED TECHNIQUES
Table 6-1a. Variable Frequency Filter Stage
program for variable frequency filter input is X,output YO, intermediate values Y I, Y2
BI =0.75 +C
B2 is realized by successive additions/subtractions, and value -0.9375 corresponding to a bandwidth of approximately
82Hz when the sample rate is 8KHz.
propagate through delay stages
LDA Y2, YI, ROO
LOA Y I YO, ROO
; generate B2*Y2 in YO
LOA YO, Y2, R4
SUB YO, Y2, RO
; set up for mUltiply
LOA DAR, C, RO
; perform multiply and add to YO
ADD YO, YI, RI,
ADD YO, YI, R2,
ADD YO, YI, R3,
ADD YO, YI, R4,
ADD YO, YI, R5,
ADD YO, YI, R6,
ADD YO, YI, R7,
ADD YO, YI, R8,
CND7
CND6
CND5
CND4
CND3
CND2
CNDI
CNDO
; add 0.75*YI to YO to complete BI *YI
ADD YO, YI, RI
ADD YO, Yl, R2
; +1I16*Y2 in YO
; -15/16*Y2 in YO
add in input to filter, scaled to prevent overflow
ADD YO, YI, R5
; filter range is 569 to 1493 Hz center frequency, resolution is 6 Hz at 569,3 Hz at 1493
Table 6-1b. Gain Compensation
in place of the last code line of table 6-la, which added in the input scaled to avoid overflow, the gain compensation
code below can be substituted:
Gain compensation-add x(c/128)
ADD YO, X, R8, CND7
ADD YO, X, R9, CND6
ADD YO, X, RIO, CND5
ADD YO, X, RII, CND4
ADD YO, X, R12, CND3
ADD YO, X, R13, CND2
; Subtract X* 111256 = X(l/32 + 11128 + 11256)
SUB YO, X, R5
SUB YO, X, R7
SUB YO, X, R8
Note-only 7 bits precision were used in the multiplication by c, to prevent the need for additional temporary RAM
locations
6-3