Intel 2920 Design Handbook page 32

THE 2920 SIGNAL PROCESSOR
The operations performed by the ALU are summarized
in Table 3-5. Although most of them are self-
explanatory, the following details may be useful at this
point.
Absolute value (ABS) and absolute add (ABA) convert
the" A" operand (source) to its absolute value before
performing any calculations. Load A (LOA) and ABS
are treated as arithmetic operations by the ALU, mean-
ing that the source is added to zero and then replaces the
"B" operand (destination). This causes the correct han-
dling of those overflows caused by left shift operations.
The operation LIM sets the result to positive or negative
full scale, based on the "A" port sign bit, behaving
much like a forced overflow. However, the overflow
flag will not indicate overflow for a LIM unless the
given source operand and shiftcode would produce an
overflow in an LOA operation.
The constant source codes allow you to select constants
for arithmetic operations. The procedure is described in
the section on the storage array of the ALU and
memory. Table 3-2 above lists the mnemonics and cor-
responding un scaled value of each constant. Each value
is passed through the scaler, and so may be multiplied
by a value 2k, where k runs from +2 to -13. The scaler
codes and equivalent multiplier values are shown in
Table 3-3.
Conditional Arithmetic Operations-In addition to
the basic operations described in Table 3-5, some ALU
functions may execute conditionally. Certain codes in
the analogi digital control field cause the execution of
the arithmetic operation to be conditional on a selected
bit of the DAR. The conditional instructions are
tabulated in Table 3-5b.
The conditional field code selects a bit of the DAR, and
uses its value to determine how the instruction is to be
executed. A "I" implies execution of the instruction; a
"0" implies execution of a NOP. For conditional sub-
tract, the bit actually used is the carry from the previous
result. In this case the selected bit of the DAR is set
equal to the carry from the current instruction.
Conditional additions are used to mUltiply one variable
by a second, as discussed in Chapter 4. The mUltiplier is
loaded into the DAR, and the multiplicand is added
conditionally to the partial product.
3-7
Conditional subtraction is used to divide one positive
variable by another, using a non-restoring division
algorithm. The divisor is conditionally subtracted from
the dividend, and quotient bits are assembled in the
DAR.
Conditional operations may also be useful for perform-
ing logic, also shown in Chapter 4. Table 3-4 sum-
marizes the properties of the arithmetic section.
Table 3-4. Memory-ALU Section Summary
ALU result bit width
Number System
Operand A
ALU instruction field
width
Scaler instruction field
width
"A" and "B" port
address field width
Ancillary Instructions
25 bits
2's complement
Read Only Memory Port A,
Scaled by shifter, 28 bits wide
Read Port B, Unsealed, 25 bits
expanded to 28 bit equivalent
3 bits
4 bits
6 bits each
ConditIonal arithmetic, op
codes are part of analog control
field
Available Storage "A" port, AdrO-39, Read Only,
Locations 25 bits. "B" port, AdrO-39,
Read-Write 25 bits.
Digital-Analog-Register "A" port, Adr40, Read Only, 9
MSBs, 16 LSB's are filled with
Is. "B" port, same as "A" port
but read-write.
Constant Register "A" port only, low 4 bits of
adr. Field placed in 4 MSB's of
25-bit width. Low 21 LSB's fill
as O's.
Scaler Range 22 (left 2) to TlJ (nght 13).
3.2.3 The Analog Section
Figure 3-5 shows a detailed block diagram of the 2920's
analog section, which provides four analog input chan-
nels and eight analog output channels. It includes
circuitry for analog-to-digital conversion by successive
approximation, and the sample-and-holds for both
inputs and outputs.