Intel 2920 Design Handbook page 84

Analog signal processor
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ADVANCED TECHNIQUES
BYTE TAKEN
DATA TAKEN
SERIAL DATA IN
DATA READY
1.SK
1.SK
SIGIN 0
SIGIN 1
2K
-'-
SIGOUT 0
SIGOUT 1
2920
VREF
M1
1
+2V
+5V
Figure 6-9. Logic Diagram for Digital Input: Serial
Input
Serial-This
example
illustrates
non-
synchronous inputs on a bit serial basis with one bit per
program pass and multiple bytes put away in the 2920
(see Figure 6-9). Table 6-7 shows the instruction
sequence.
The BYTE TAKEN signal may be used for BYTES
TAKEN by having it asserted on the reset of CT2 rather
than CTI.
Transfers Between Two 2920's-When two or more
2920's are used together digital parameters may need to
be passed between them. The obvious method would
seem to be to output an analog representation of the
IOF
2920
#1
X1y21
I
EOP
1
EXT elK
ExTCLi<
S.6K
number which is converted back in the receiving 2920.
This method is limited to about four bits per transfer
because the effective gain between an output and an
input is approximately 0.9. Generally fewer instructions
and/or greater speed result if the overflow is used for
outputting and one bit conversion made on input. The
input analog sample time is reduced if only a binary
decision is made and the lengthy output sequence is
avoided with the use of the overflow pin.
The previous examples of serial output and input may
be used for the program sequence. Synchronism of the
two programs is assured within seven instructions by the
paralleled EOP signals and use of the same external
clock. Exact synchronization is possible with external
logic. (See Figure 6-10.)
T
+sv
3.3K
SIGIN 0
2920
2K
#2
~
+2V
~
xllx2T 1
EOP
I
I
Figure 6-10. Synchronizing Multiple 2920s
6-11

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