Intel 2920 Design Handbook page 83

ADVANCED TECHNIQUES
Table 6-6.
Digital Input:
Parallel-Serial
Instruction Sequence.
LDA
D, KPO
LDA DAR, KPO
aUTO Enable parallel load
OUTl
Enable clock
LDA DAR, KP7 Clear parallel load
aUTO
LDA DAR, KP2 DAR =
FS/4
INO Input D7
CVT3
LDA R, KP7,
Ll
OF clocks shift register
INO
Input D6
CVT2
LDA R, KP7, Ll Repeat through D4
CVTO
LDA
R, KP7, Ll
SUB DAR, KP2 DAR contains 07-04
LDA
0, OAR, L2 Left shift OAR two bits into D
LOA OAR, KP2 Repeat for 03-00
INO
CVT3
LDA R, KP7, Ll
CVTO
SUB DAR, KP2 DAR contains 03-00
XOR
DAR, D, L2 OAR contains 00-07
LOA D, DAR Load 07-00 into D
LOA OAR, KP7
OUTl Disable clock
Summary:
Analog instructions 8A+3B+8C
Oigital instructions 19
Input pins I
Output pins 2
Oata memory locations
2
Overflow Affected
6-10