Intel 2920 Design Handbook page 108

DESIGN CONSIDERATIONS
Symbol Function
SIGOUT
8 pins corresponding to the 8 demulti-
plexed analog outputs (0-7).
GRDA Analog signal ground held at or near
GRDD typically.
CAP, & CAP2 External capacitor connections for the
Input signal sample and hold circuit
VREF Input Reference Voltage.
SIGIN
4 pins corresponding to the 4 multi-
plexed analog Inputs (0-3).
Vss Most negative power pin set at -5 volts
during run mode (different voltage in
program mode)
X1/CLK Clock input when using external clock
signals, OSCillator input for external
crystal when using internal clock.
X2
OSCillator input for external crystal when
using internal clock.
GRDD Digital ground
Vee
5 volts in run mode.
CCLK
Internal fetch cycle clock output. The
falling edge designates the START of a
new PROM fetch cycle. CCLK is 1/16 of
X1/CLK rate.
RUN/PROG Mode control tied to GRDD in run mode
(different voltage in program mode).
RST/EOP
Low RST input initializes program fetch
counter to first location. As an output it
signifies EOP instruction present (open
drain, active low).
Symbol
OF
VSP
M1, M2
Function
Indicates an overflow in the current ALU
operation (open drain, active low).
EPROM powerPrnOvoltsforRUN mode.
(Different voltage in program mode).
Two pins which specify the output mode
of the SIGOUT pins (see Table 4).
SIGOUT 3 SIGOUT 2
SIGOUT 4 SIGOUT 1
SIGOUT 5 SIGOUT 0
GRDA
Ml
SIGOUT 6
M2
SIGOUT 7 VSP
CAP!
OJ!
VREF RST/EOP
CAP 2 RUN/PROG
SIGINO CClK
SIGIN 3 Vee
Vee
GRDO
SIGIN 2
X 2
SIGIN 1 XI/ClK
Figure 8-2. 2920 Pinout
c) Isolate the sample and hold capacitor from all
signals to prevent noise from coupling into the chip.
d) Use a separate digital and analog ground, and tie
them together close to the power supply ground.
e) Isolate the clock input from all other signals.
f) Avoid ground loops and use heavy gauge wire for
grounds and supply voltages.
g) Keep the analog input and output leads short and
separated.
8-3
h) Keep the clock wires short and use heavy gauge wire
for the clock signals.
Table 8-1. Output Mode For Signout Pins As
Function Of M1 And M2
M1
M2
Signout Pins
5V 5V
0-7 Analog
5V -5V
0-3 Analog, 4-7 TTL
-5V 5V
0-3 TTL, 4-7 Analog
-5V -5V
0-7 TTL