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CHAPTER8
DESIGN CONSIDERATIONS
8.0 DESIGN CONSIDERATIONS
8.1 2920 Debugging Procedures
After all aspects of the program have been tested under
control of the Simulator, the designer programs the
2920 EPROM and plugs it into the breadboard. If it
does not function as desired, troubleshooting must
begin. This section outlines some basic procedures for
debugging the 2920 and its environment.
Where To Start-The 2920 includes some useful
digital outputs for many signal processing applications.
These EOP, CCLK, and OF signals can be of great
value during debugging phases.
Check that the required plus and minus 5 volt supplies
appear at pin 18 and 12. respectively. A scope won't
necessarily reveal if GRDD is connected, since scope
ground and GRDD are the same potential. This also
holds true for VSP and RUN. Check them also.
Look at CCLK. CCLK is the instruction execution rate
clock, and its period should be one-sixteenth the
crystal/clock rate at Xl and X2. CCLK's pulse width
should be about one instruction cycle. If CCLK is at or
near GRDD potential almost all the time, check that
there is a pullup resistor (and that it is connected prop-
erly). If CCLK is still not working appropriately, it is
likely that the master clock at Xl and X2 is not
adequate.
For clock operation with crystal, a capacitor of approx-
imately 15 pf is required between X2 and VBB. Stray
capacitances must also be considered, i.e., the sum of all
X2 capacitances to VBB should be no more than 15 pf,
and X 1 to X2 stray capacitance should not exceed 15 pf
also. In general, good wiring practices will avoid any
problems with the operation of a crystal.
Operating the 2920 with an external clock source
requires some care. X 1 and X2 should be driven with
true-complement signals, and the circuit in Figure 8-1 is
recommended. The key starting point for the 2920's
high speed operation is the master clock. Timing
requirements include a duty cycle of 50±5 0/0, or better,
and a rise or fall time of less than 5 nanoseconds.
Voltage "high" levels should be greater than -1 volt,
and "low" levels less than -4 volts. Rise and fall times
should be measured between -1 and -4 volts. (TTL
with V cc
=
-·5 V .) If CCLK is jittery or erratic, the prob-
lem is usually in the master clock.
8-1
INPUT
010 -5
VOLTS
GRDD
-5V
47011
D--4~
_ _ _ _
--,1""15 XTAL1
GRDD
-5V
47011
,--_~~_....:.1=i6
XTAL2
Figure
8-1.
Driving From External Source
If the program results do not agree with simulation
results, there are a number of things to review.
Noise on the VREF supply will contribute to many
problems. In general,
it
is good practice to keep VREF
noise to less than 4mv. Any noise greater than 4mv
could cause AID conversion errors, which can result in
stability problems in digital filters. The same holds true
for the GRDA pin.
Although the 2920 processes analog signals using digital
techniques, the hardware designer developing a 2920-
based product must always keep in mind that the
device's primary interface is analog. In effect, standards
applying to breadboard or printed circuit layout for
analog circuitry still apply to 2920 environments. In
general, special consideration to ground planes, guard
rings, power supply bypassing, and digital isolation
from analog signals are required to achieve optimal
2920 performance.
Analog Ground Plane-The GRDA and GRDD leads
are not connected internally in the 2920. A connection
outside the device is necessary to tie all analog ground
lines to the common return of the system ground. That
external GRDA to GRDD connection should be such
that the GRDA connection is minimal impedance (a
ground plane) to help minimize digital noise being
induced into the 2920's analog section.
Power Supply Bypassing- In general, standard
power supply bypass techniques for analog circuits
should be used. The ±5 volt power pins inside the 2920
are connected to both the digital
and
analog circuitry.
Although the analog components exhibit good power
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