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ADVANCED TECHNIQUES
+5V
5.6k
+2V
VREF
SIGOUT 7
07
M2
2920
74364
~
REGISTER
SIGOUT 0
+5V
DO
DATA OUT
1\
lEap
I
CLOCK
Figure 6·4. Logic Diagram for Digital Output: Parallel
With a 10 MHz clock and B=5, the total of 65 instruc-
tions for output would provide a maximum of 38 K
bytes/second transfer rate. With a full length program
this would be reduced by a factor of three.
Output Serial-For synchronous parallel output of
one byte using serial transfer out of the 2920 overflow
(OF) pin. Multiple bytes per program pass can be out-
putted with the 2920 as master and one control signal,
(see Figure 6-5). Table 6-4 shows the instruction
sequence.
Table 6·4. Digital Output: Serial
Instruction Sequence.
Instruction sequence.
LDA
DAR,
KP7
OUTO
LDA
DAR,
DATA
3
LDA
R,
KPO
0
LDA
R,
KP4,
1
NOP
2
LDA
R,
R,
LDA
R,
KPO
LDA
R,
KP4,
LDA
DAR,
KPO
LDA
R,
R,
OUTO
Summary:
Analog instructions
Digital instructions
Input pins
Output pins
Data memory location
Overflow
Set DATA VALID
Load byte of data into DAR
Set R = 0
CNDO
R=O.5 if data bit 0 is 1
L2
Overflow if bit 0 was 1
Repeat sequence through bit 7
CND7
L2
Overflow if bit 7 was 1
Clear DATA VALID
8+2B
19
o
1
1
Affected during I/O
6-6
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